LCMXO2280C-4TN144I Lattice, LCMXO2280C-4TN144I Datasheet - Page 95

• Manufacturer Part Number: LCMXO2280C-4TN144I
• Description: CPLD - Complex Programmable Logic Devices 2280 LUTs 113 IO 1.8 /2.5/3.3V -4 Spd I
• Manufacturer: Lattice

Specifications of LCMXO2280C-4TN144I

• Rohs: yes
• Memory Type: SRAM
• Number Of Macrocells: 1140
• Maximum Operating Frequency: 550 MHz
• Delay Time: 4.4 ns
• Number Of Programmable I/os: 113
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 300
• Supply Current: 23 mA
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 1.71 V

www.latticesemi.com
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
October 2005
For Further Information
A variety of technical notes for the MachXO family are available on the Lattice web site at www.latticesemi.com.
For further information on interface standards refer to the following web sites:
• MachXO sysIO Usage Guide (TN1091)
• MachXO sysCLOCK PLL Design and Usage Guide (TN1089)
• MachXO Memory Usage Guide (TN1092)
• Power Calculations and Considerations for MachXO Devices (TN1090)
• MachXO JTAG Programming and Configuration User’s Guide (TN1086)
• Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)
• MachXO Density Migration (TN1097)
• IEEE 1149.1 Boundary Scan Testability in Lattice Devices
• JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
• PCI: www.pcisig.com
6-1
MachXO Family Data Sheet
Supplemental Information
Further Information_01.1
Data Sheet