LC4256V-75FT256AI Lattice, LC4256V-75FT256AI Datasheet - Page 24

• Manufacturer Part Number: LC4256V-75FT256AI
• Description: CPLD - Complex Programmable Logic Devices ispJTAG 3.3V 7.5ns 256MC 128 I/O IND
• Manufacturer: Lattice

Specifications of LC4256V-75FT256AI

• Memory Type: EEPROM
• Number Of Macrocells: 256
• Maximum Operating Frequency: 178.57 MHz
• Delay Time: 7.5 ns
• Number Of Programmable I/os: 160
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Package / Case: FTBGA
• Mounting Style: SMD/SMT
• Number Of Product Terms Per Macro: 80
• Factory Pack Quantity: 450
• Supply Current: 12.5 mA
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

Lattice Semiconductor
ispMACH 4000Z External Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
PD
PD_MC
S
ST
SIR
SIRZ
H
HT
HIR
HIRZ
CO
R
RW
PTOE/DIS
GPTOE/DIS
GOE/DIS
CW
GW
WIR
MAX
MAX
Parameter
4
(Ext.)
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay
through macrocell
GLB register setup time before clock
GLB register setup time before clock with
T-type register
GLB register setup time before clock, input
register path
GLB register setup time before clock with zero
hold
GLB register hold time after clock
GLB register hold time after clock with T-type
register
GLB register hold time after clock, input
register path
GLB register hold time after clock, input
register path with zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output
enable/disable
Input to output global product term output
enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transparent) or
high (for high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
clock frequency with external feedback,
[1 / (t
S
+ t
CO
)]
Description
Over Recommended Operating Conditions
1, 2, 3
24
Min.
2.2
2.4
1.0
2.0
0.0
0.0
1.0
0.0
1.5
1.0
1.0
1.0
—
—
—
—
—
—
—
—
—
ispMACH 4000V/B/C/Z Family Data Sheet
-35
Max.
267
192
3.5
4.4
3.0
5.0
7.0
6.5
4.5
—
—
—
—
—
—
—
—
—
—
—
—
Min.
2.5
2.7
1.1
2.1
0.0
0.0
1.0
0.0
1.7
1.5
1.5
1.5
—
—
—
—
—
—
—
—
—
-37
Max.
250
175
3.7
4.7
3.2
6.0
8.0
7.0
4.5
—
—
—
—
—
—
—
—
—
—
—
—
Min.
2.7
2.9
1.3
2.6
0.0
0.0
1.3
0.0
2.0
1.8
1.8
1.8
—
—
—
—
—
—
—
—
—
-42
Max.
220
161
4.2
5.7
3.5
7.3
8.0
8.0
4.8
—
—
—
—
—
—
—
—
—
—
—
—
Timing v.2.2
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns