MAX11205BEUB+T Maxim Integrated, MAX11205BEUB+T Datasheet - Page 9

• Manufacturer Part Number: MAX11205BEUB+T
• Description: Analog to Digital Converters - ADC 16-Bit Delta-Sigma
• Manufacturer: Maxim Integrated

Specifications of MAX11205BEUB+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: Sigma-Delta
• Conversion Rate: 120 SPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Interface Type: SPI
• Operating Supply Voltage: 1.7 V to 3.6 V, 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 444 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 3.6 V

The MAX11205 is an ultra-low power (< 240FA active),
high-resolution, low-speed, serial-output ADC. This device
provides the highest resolution per unit power in the
industry, and is optimized for applications that require
very high dynamic range with low power such as sensors
on a 4mA to 20mA industrial control loop.
The MAX11205 provides a high-accuracy internal oscilla-
tor, which requires no external components. When used
with the specified data rates, the internal digital filter pro-
vides more than 80dB rejection of 50Hz or 60Hz line noise.
The MAX11205 provides a simple, system-friendly, 2-wire
serial interface in the space-saving, 10-pin FMAX package.
The MAX11205 utilizes power-on reset (POR) supply-
monitoring circuitry on both the digital supply (DVDD)
and the analog supply (AVDD). The POR circuitry
ensures proper device default conditions after either a
digital or analog power-sequencing event.
The MAX11205 performs a self-calibration operation as
part of the startup initialization sequence whenever a
digital POR is triggered. It is important to have a stable
reference voltage available at the REFP and REFN pins
to ensure an accurate calibration cycle. If the reference
voltage is not stable during a POR event, the part should
be calibrated once the reference has stabilized. The part
can be programmed for calibration by using 26 SCLKs
as shown in Figure 3.
The digital POR trigger threshold is approximately 1.2V
and has 100mV of hysteresis. The analog POR trigger
threshold is approximately 1.25V and has 100mV of hys-
teresis. Both POR circuits have lowpass filters that pre-
vent high-frequency supply glitches from triggering the
POR. The analog supply (AVDD) and the digital supply
(DVDD) pins should be bypassed using 0.1FF capaci-
tors placed as close as possible to the package pin.
The MAX11205 accepts two analog inputs (AINP and
AINN). The modulator input range is bipolar (-V
+V
The MAX11205 incorporates a highly stable internal
oscillator that provides the system clock. The system
clock runs the internal state machine and is trimmed to
2.4576MHz (MAX11205A) or 2.2528MHz (MAX11205B).
REF
Delta-Sigma ADC with 2-Wire Serial Interface
).
16-Bit, Single-Channel, Ultra-Low Power,
_______________________________________________________________________________________
Detailed Description
Power-On Reset (POR)
Internal Oscillator
Analog Inputs
REF
to
The internal oscillator clock is divided down to run the
digital and analog timing.
The MAX11205 provides differential inputs REFP and
REFN for an external reference voltage. Connect the
external reference directly across REFP and REFN to
obtain the differential reference voltage. The common-
mode voltage range for V
and V
REFN is 1V to V
The MAX11205 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC
operating in single-cycle conversion mode, the filter is
reset at the end of the conversion cycle. When operat-
ing in continuous conversion latent mode, the filter is not
reset. The SINC
24% of the data rate.
The MAX11205 communicates through a 2-wire serial
interface with a clock input and data output. The output
rate is predetermined based on the package option
(MAX11205A at 120sps and MAX11205B at 13.75sps).
The MAX11205 is compatible with the 2-wire interface
and uses SCLK and RDY/DOUT for serial communica-
tions. In this mode, all controls are implemented by tim-
ing the high or low phase of the SCLK. The 2-wire serial
interface only allows for data to be read out through the
RDY/DOUT output.
Supply the serial clock to SCLK to shift the conversion
data out.
The RDY/DOUT is used to signal data ready, as well as
reading the data out when SCLK pulses are applied.
RDY/DOUT is high by default. The MAX11205 pulls
RDY/DOUT low when data is available at the end of con-
version, and stays low until clock pulses are applied at
SCLK input; on applying the clock pulses at SCLK, the
RDY/DOUT outputs the conversion data on every SCLK
positive edge. To monitor data availability, pull RDY/
DOUT high after reading the 16 bits of data by supplying
a 25th SCLK pulse.
The different operational modes using this 2-wire inter-
face are described in the following sections.
AVDD
. The differential voltage range for REFP and
4
AVDD
(sinx/x)
4
filter has a -3dB frequency equal to
.
4
response. When the device is
REFP
Serial-Digital Interface
and V
REFN
2-Wire Interface
Digital Filter
Reference
is between 0
9