ADC1213D080HN-C1 IDT, ADC1213D080HN-C1 Datasheet
ADC1213D080HN-C1
Specifications of ADC1213D080HN-C1
Related parts for ADC1213D080HN-C1
ADC1213D080HN-C1 Summary of contents
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... Compliant with JESD204A serial transmission standard Pin compatible with the ADC1613D series, ADC1413D series, and ADC1113D125 Product data sheet Input bandwidth, 600 MHz Power dissipation, 995 Msps SPI register programming Duty cycle stabilizer (DCS) ...
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... Ultrasound equipment 4. Ordering information Table 1. Ordering information Type number Sampling frequency (Msps) ADC1213D125HN-C1 125 ADC1213D105HN-C1 105 ADC1213D080HN-C1 80 ADC1213D065HN-C1 65 ADC1213D_SER 8 Product data sheet Dual 12-bit ADC; serial JESD204A interface Portable instrumentation Imaging systems Software defined radio Package ...
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... Rev. 08 — 2 July 2012 ADC1213D series SYNCP SYNCN SWING_n SERIALIZER A CMLPA 10-bit OUTPUT CMLNA BUFFER A CMLPB SERIALIZER B 10-bit OUTPUT CMLNB BUFFER B SWING_n SYSTEM REFERENCE AND POWER MANAGEMENT REFAB REFBB REFAT VCMB VCMA SENSE VREF 005aaa120 © IDT 2012. All rights reserved ...
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... O channel B bottom reference 11 O channel B top reference 12 O channel B output common voltage Rev. 08 — 2 July 2012 ADC1213D series 42 DGND 41 DGND 40 VDDD 39 CMLPA 38 CMLNA 37 VDDD 36 DGND 35 DGND 34 VDDD 33 CMLNB 32 CMLPB 31 VDDD 30 DGND 29 DGND 005aaa121 © IDT 2012. All rights reserved ...
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... JESD204 serial buffer programmable output swing 48 I JESD204 serial buffer programmable output swing not connect 50 P analog power supply analog ground 52 G analog ground Rev. 08 — 2 July 2012 ADC1213D series [2] [2] © IDT 2012. All rights reserved ...
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... Msps - clk Rev. 08 — 2 July 2012 ADC1213D series Min Max Unit 0.4 +4.6 V 0.4 +2.5 V 55 C +125 40 C +85 C - 125 Conditions Typ Unit [1] 17.8 K/W [1] 6.8 K/W Typ Max Unit 3.0 3.4 V 1.8 1.95 V 343 - mA 150 - mA 1270 - mW 1150 - mW 995 - mW 885 - mW © IDT 2012. All rights reserved ...
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... Max 30 - 200 - 0.8 - 1 0.3V DDA - - DDA 0 - 0.66V - DDD - +6 - +30 - 0.3V DDA - V DDA DDA - + 1.5 2 600 - - DDA 4 - © IDT 2012. All rights reserved. Unit A A A pF A MHz ...
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... Rev. 08 — 2 July 2012 ADC1213D series Typ Max Unit - pin AGND VREF DDA 1.275 - V 1 1.625 - 1.125 - V 1 1.575 - LSB 0.5 +0.95 LSB 0 © IDT 2012. All rights reserved ...
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... Minimum and maximum values are across the full temperature = 1 DDD amb (INAP, INBP) 1 DDD I Rev. 08 — 2 July 2012 ADC1213D series Typ Max 1.1 - 54 - (INAM, INBM) = 1 dBFS; internal reference mode; I © IDT 2012. All rights reserved. Unit % ...
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Dynamic characteristics 10.1 Dynamic characteristics Table 6. Dynamic characteristics [1] Symbol Parameter Conditions Analog signal processing second harmonic level MHz MHz MHz 170 ...
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Table 6. Dynamic characteristics [1] …continued Symbol Parameter Conditions IMD intermodulation distortion MHz MHz MHz 170 MHz i channel crosstalk MHz ct(ch) ...
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... DC coupling with two different receiver common-mode voltages Fig 3. Eye diagram receiver common-mode Fig 4. Eye diagram receiver common-mode ADC1213D_SER 8 Product data sheet ADC1213D series Dual 12-bit ADC; serial JESD204A interface Rev. 08 — 2 July 2012 005aaa088 005aaa089 © IDT 2012. All rights reserved ...
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... Dual 12-bit ADC; serial JESD204A interface Min Typ Max - C. Minimum and maximum values are amb = 1 DDA DDD I t w(SCLKL w(SCLKH) A11 005aaa065 . DDA © IDT 2012. All rights reserved. Unit MHz (INAP ...
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... The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. Fig 7. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. ADC1213D_SER 8 Product data sheet Dual 12-bit ADC; serial JESD204A interface package ...
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... Rev. 08 — 2 July 2012 ADC1213D series Capacitance (pF Ω INAP INBP 25 Ω Ω 25 Ω INAM INBM VCM 100 nF 005aaa070 12 Ω INAP INBP 50 Ω 8 Ω 12 Ω INAM INBM VCM 100 nF 005aaa071 © IDT 2012. All rights reserved ...
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... VREF pin = SENSE pin and 330 pF capacitor to GND Rev. 08 — 2 July 2012 ADC1213D series REFAT/ REFBT REFAB/ REFBB BANDGAP REFERENCE ADC CORE VREF pin Full-scale (V (p-p)) 330 pF capacitor 2 to GND 1 external voltage from 0 © IDT 2012. All rights reserved ...
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... Programmable full-scale Level (dB) 0 1 2 3 4 5 6 not used O(cm) Rev. 08 — 2 July 2012 ADC1213D series VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE 005aaa117 VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE 005aaa118 Full-scale (V (p-p)) 2 1.78 1.59 1.42 1.26 1. © IDT 2012. All rights reserved ...
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... I(cm) CLKP LVCMOS clock input CLKM 005aaa174 Rev. 08 — 2 July 2012 ADC1213D series Dual 12-bit ADC; serial JESD204A interface COMMON MODE REFERENCE ADC CORE 005aaa077 CLKP CLKM LVCMOS clock input 005aaa053 b. Falling edge LVCMOS © IDT 2012. All rights reserved ...
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... Rev. 08 — 2 July 2012 ADC1213D series Dual 12-bit ADC; serial JESD204A interface Sine clock input b. Sine clock input (with transformer) CLKP CLKM 005aaa172 V cm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ 005aaa081 © IDT 2012. All rights reserved. CLKP CLKM 005aaa054 ...
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... Dual 12-bit ADC; serial JESD204A interface Duty cycle stabilizer VDDD 50 Ω CMLPA/CLMPB CMLNA/CLMNB − + AGND Rev. 08 — 2 July 2012 ADC1213D series Description duty cycle stabilizer disable duty cycle stabilizer enable 100 Ω RECEIVER 005aaa082 © IDT 2012. All rights reserved ...
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... OCTETS TX CONTROLLER FRAME F octets TO SCRAMBLER OCTETS Lx(F) octets L octets Rev. 08 — 2 July 2012 ADC1213D series 100 Ω RECEIVER 005aaa083 ALIGNMENT 8-bit/ SER CHARACTER 10-bit GENERATOR ALIGNMENT 8-bit/ CHARACTER SER 10-bit GENERATOR 005aaa084 © IDT 2012. All rights reserved. LANE 0 LANE ...
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... IDT 2012. All rights reserved. 005aaa175 OTR ...
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... A12 A11 A10 Number of bytes transferred 1 byte 2 bytes 3 bytes 4 or more bytes © IDT 2012. All rights reserved. OTR LSB ...
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... In read mode only A is active. ADC1213D_SER 8 Product data sheet Dual 12-bit ADC; serial JESD204A interface Register N (data) Rev. 08 — 2 July 2012 ADC1213D series Register (data) © IDT 2012. All rights reserved 005aaa086 ...
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Table 17. Register allocation map [1] Address Register name Access (hex) Bit 7 ADC control register 0003 Channel index R/W - 0005 Reset and R/W SW_ Power-down RST modes 0006 Clock R/W - 0008 Vref R/W - 0013 Offset R/W ...
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Table 17. Register allocation map …continued [1] Address Register name Access (hex) Bit 7 0824 Cfg_5_K R/W* 0 0825 Cfg_6_M R/W* 0 0826 Cfg_7_CS_N R/W* 0 0827 Cfg_8_Np R/W 0 0828 Cfg_9_S R/W* 0 0829 Cfg_10_HD_CF R/W* HD 082C Cfg_01_2_LID ...
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... SE clock input pin: 0 select CLKM input 1 select CLKP input differential/single-ended clock input select: 0 fully differential 1 single-ended 0 not used select clock input divider disable 1 active Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... V) 1 dB (FS=1.78 V) 001 2 dB (FS=1.59 V) 010 3 dB (FS=1.42 V) 011 4 dB (FS=1.26 V) 100 5 dB (FS=1.12 V) 101 6 dB (FS=1 V) 110 111 not used Rev. 08 — 2 July 2012 ADC1213D series +31 LSB ... 0 ... 32 LSB © IDT 2012. All rights reserved ...
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... Value Description 0 initiates a software reset of the JESD204Aunit 000 not used 0 initiates a software reset of the internal state machine of JESD204A unit 000 not used Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... K) K) K) K) test: loop 1 alignment 2 2 chip 1 power-down © IDT 2012. All rights reserved. [1] [ ...
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... JESD204A unit (ADC A output is connected to ADC input B, ADC B is connected to ADC input A): 0 disable 1 enable Value Description 00000 not used 011 defines the swing output for the lane pads Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... Value Description 0 scrambling enabled 000000 not used 0 defines the number of lanes per converter device, minus 1 Value Description 00000 not used 001 defines the number of octets per frame, minus 1 Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... Description 0 defines high density format 00000 not used 00 defines number of control words per frame clock cycle per link Value Description 000 not used 11011 defines lane 0 identification number Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... ADC output is connected to the JESD204A input 01 not used 10 JESD204A input is fed with a dummy constant, set to: OTR = 0 and ADC[11:0] = “100110111010” 11 JESD204A is fed with a PRBS generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register) Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... ADC[11:0] = “100110111010” 11 JESD204A is fed with a PRBS generator (PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_ctrl register) 000 not used ADC power-down control: 0 ADC is operational 1 ADC is in Power-down mode Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... 5.95 8.1 6.55 0.5 5.80 8.0 6.40 0.5 6.5 6.5 0.4 5.65 7.9 6.25 0.3 References JEDEC JEITA - - - MO-220 Rev. 08 — 2 July 2012 ADC1213D series Dual 12-bit ADC; serial JESD204A interface detail 0.1 0.05 0.05 0.1 European Issue date projection 08-11-19 09-03-04 © IDT 2012. All rights reserved. SOT684-7 sot684-7_po ...
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... Low Voltage Complementary Metal Oxide Semiconductor Low-Voltage Positive Emitter-Coupled Logic Most Significant Bit OuT-of-Range Pseudo-Random Binary Sequence Spurious-Free Dynamic Range Signal-to-Noise Ratio Serial Peripheral Interface Transmitter Rev. 08 — 2 July 2012 ADC1213D series © IDT 2012. All rights reserved ...
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... Objective data sheet 20090617 Objective data sheet 20090604 Objective data sheet 20090528 Objective data sheet http://www.idt.com Rev. 08 — 2 July 2012 ADC1213D series Change Supersedes notice - ADC1213D_SER v.7 - ADC1213D_SER v.6 - ADC1213D_SER v.5 - ADC1213D_SER v.4 - ADC1213D065_080_105_125 v.3 - ADC1213D065_080_105_125 v.2 - ADC1213D065_080_105_125 v © IDT 2012. All rights reserved ...
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... Serial Peripheral Interface (SPI 11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 23 11.6.2 Channel control . . . . . . . . . . . . . . . . . . . . . . . 24 11.6.3 Register description . . . . . . . . . . . . . . . . . . . . 27 11.6.3.1 ADC control register 11.6.4 JESD204A digital control registers . . . . . . . . 29 12 Package outline Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 39 15 Contact information . . . . . . . . . . . . . . . . . . . . 39 16 Contents Rev. 08 — 2 July 2012 ) . . . . . 17 O(cm) © IDT 2012. All rights reserved ...