MAX159BCUA+T Maxim Integrated, MAX159BCUA+T Datasheet - Page 10

• Manufacturer Part Number: MAX159BCUA+T
• Description: Analog to Digital Converters - ADC 10-Bit 108ksps 5.25V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX159BCUA+T

• Rohs: yes
• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 108 KSPs
• Resolution: 10 bit
• Input Type: Pseudo-Differential
• Snr: No
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 727 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 5.25 V

Table 1 illustrates the 16-bit, serial data-stream output
format for both the MAX157 and MAX159. The first three
bits are always logic high (including the EOC bit for
internal clock mode), followed by the channel identifica-
tion (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 1 for
MAX159), the 10 bits of data in MSB first format, and
two sub-LSB bits (S1 and S0). After the last bit has been
read out, additional SCLK pulses will clock out trailing
zeros. DOUT transitions on the falling edge of SCLK.
The output remains high impedance when CS/SHDN is
high.
An external reference is required for both the MAX157
and MAX159. At REF, the DC input resistance is a mini-
mum of 18kΩ. During a conversion, a reference must
be able to deliver 250µA of DC load current and have
an output impedance of 10Ω or less. Use a 0.1µF
bypass capacitor for best performance. The reference
input structure allows a voltage range of 0 to (V
50mV) although noise levels will decrease effective res-
olution at lower reference voltages.
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
Figure 6. External Clock Mode Timing
Figure 7. Detailed Serial-Interface Timing Sequence
10
CS/SHDN
DOUT
SCLK
______________________________________________________________________________________
CS/SHDN
HIGH-Z
DOUT
SCLK
ACTIVE
t
SCLKS
HIGH-Z
POWER
DOWN
t
CS
t
DV
ACTIVE
Output Data Format
External Reference
t
(t
WAKE
ACQ
)
SAMPLING INSTANT
1
t
CL
2
3
t
CHID
CH
DD
4
MSB
5
+
D8
6
D7
Whenever the MAX157/MAX159 are not selected
(CS/SHDN = V
In shutdown all internal circuitry is turned off, which
reduces the supply current to typically less than 0.2µA.
With an external reference stable to within 1LSB, the
wake-up time is 2.5µs. If the external reference is not sta-
ble within 1LSB, the wake-up time must be increased to
allow the reference to stabilize.
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
7
D6
8
D5
9
D4
10
SNR
D3
11
DD
t
DO
Applications Information
(MAX)
), the parts enter their shutdown mode.
D2
Automatic Power-Down Mode
12
Signal-to-Noise Ratio (SNR)
D1
13
= (6.02 · N + 1.76)dB
D0
14
S1
15
S0
16
t
HIGH-Z
TR
t
CS
HIGH-Z