MAX11624EEG+T Maxim Integrated, MAX11624EEG+T Datasheet - Page 19

• Manufacturer Part Number: MAX11624EEG+T
• Description: Analog to Digital Converters - ADC 10-Bit 16Ch 300ksps 5V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11624EEG+T

• Rohs: yes
• Number Of Channels: 16
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended
• Interface Type: 3-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eight and ninth cycles, the pulse
width must be less than 100µs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
If reference mode 00 is requested, wait 65µs with CS
high after writing the conversion byte to extend the
acquisition and allow the internal reference to power up.
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Figure 8 shows the unipolar transfer function for single-
ended inputs. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary,
with 1 LSB = V
Figure 7. Clock Mode 11
DIN
DOUT
SCLK
EOC
CS
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Partial Reads and Partial Writes
REF
/1024 for unipolar operation.
______________________________________________________________________________________
(ACQUISITION1)
Transfer Function
with FIFO and Internal Reference
(CONVERSION BYTE)
MSB1
(CONVERSION1)
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
For best performance, use PCBs. Do not use wire wrap
boards. Board layout should ensure that digital and
analog signal lines are separated from each other. Do
not run analog and digital (especially clock) signals
parallel to one another or run digital lines underneath
the package. High-frequency noise in the V
supply can affect performance. Bypass the V
with a 0.1µF capacitor to GND, close to the V
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, connect a
10Ω resistor in series with the supply to improve power-
supply filtering.
10-Bit, 300ksps ADCs
11 . . .
11 . . .
11 . . .
00 . . .
00 . . .
00 . . .
00 . . .
. . . 111
. . . 110
. . . 101
. . . 011
. . . 010
. . . 001
. . . 000
OUTPUT CODE
(COM)
0
Layout, Grounding, and Bypassing
1
LSB1
2
INPUT VOLTAGE (LSB)
(ACQUISITION2)
3
FULL-SCALE
TRANSITION
FS - 3/2 LSB
1 LSB =
FS = V
ZS = V
MSB2
FS
REF
COM
1024
V
DD
DD
REF
+ V
DD
COM
REF
supply
power
pin.
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