MAX195BC/D Maxim Integrated, MAX195BC/D Datasheet - Page 13

• Manufacturer Part Number: MAX195BC/D
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX195BC/D

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 85 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 842 mW
• Number Of Converters: 1
• Voltage Reference: 5 V

The REF and AIN signals should not exceed the
MAX195 supply rails. If this can occur, diode clamp the
signal to the supply rails. Use silicon diodes and a 10Ω
current-limiting resistor (Figures 10 and 12) or Schottky
diodes without the resistor.
When using the current-limiting resistor, place the resis-
tor between the appropriate input (AIN or REF) and any
bypass capacitor. While this results in AC transients at
the input due to dynamic input currents, the transients
settle quickly and do not affect conversion results.
Improperly placing the bypass capacitor directly at the
input forms an RC lowpass filter with the current-limiting
resistor, which averages the dynamic input current and
causes linearity errors.
The MAX195 uses a capacitive DAC that provides an
inherent track/hold function. The input impedance is
typically 30Ω in series with 250pF in unipolar mode and
50Ω in series with 125pF in bipolar mode.
The analog input range can be either unipolar (0V to
V
state of the BP/UP/SHDN pin (see Digital Interface sec-
tion). The reference range is 0V to VDDA. When choos-
ing the reference voltage, the equivalent MAX195 input
noise (40µV
mode) should be considered.
Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence
REF
) or bipolar (-V
RMS
in unipolar mode, 80µV
REF and AIN Input Protection
SIGNAL
16-Bit, 85ksps ADC with 10µA Shutdown
______________________________________________________________________________________
INPUT
REF
to V
REF
+15V
-15V
), depending on the
Analog Input
RMS
Input Range
CLAMPS
in bipolar
1N914
DIODE
10
Four conversion-clock periods are allocated for acquir-
ing the input signal. At the highest conversion rate, four
clock periods is 2.4µs. If more than three clock cycles
have occurred since the end of the previous conver-
sion, conversion begins on the next falling clock edge
after CONV goes low. Otherwise, bringing CONV low
begins a conversion on the fourth falling clock edge
after the previous conversion. This scheme ensures the
minimum input acquisition time is four clock periods.
Most applications require an input buffer amplifier. If
the input signal is multiplexed, the input channel should
be switched near the beginning of a conversion, rather
than near the end of or after a conversion (Figure 13).
This allows time for the input buffer amplifier to respond
to a large step change in input signal. The input amplifi-
er must have a high enough slew rate to complete the
required output voltage change before the beginning of
the acquisition time.
At the beginning of acquisition, the capacitive DAC is
connected to the amplifier output, causing some output
disturbance. Ensure that the sampled voltage has set-
tled to within the required limits before the end of the
acquisition time. If the frequency of interest is low, AIN
can be bypassed with a large enough capacitor to
charge the capacitive DAC with very little change in
voltage (Figure 14). However, for AC use, AIN must be
driven by a wideband buffer (at least 10MHz), which
must be stable with the DAC’s capacitive load (in paral-
lel with any AIN bypass capacitor used) and also must
settle quickly (Figure 15 or 16).
AIN
MAX195
VDDA
VSSA
+5V
-5V
Input Acquisition and Settling
13