MAX1444EHJ/V+T Maxim Integrated, MAX1444EHJ/V+T Datasheet - Page 11

• Manufacturer Part Number: MAX1444EHJ/V+T
• Description: Analog to Digital Converters - ADC 10-Bit 40Msps 3.0V Low-Power ADC with Internal Reference
• Manufacturer: Maxim Integrated

Specifications of MAX1444EHJ/V+T

• Number Of Channels: 1
• Architecture: Pipeline
• Conversion Rate: 40 MSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: 59.5 dB
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Power Dissipation: 1495.3 mW
• Number Of Converters: 1
• Voltage Reference: 1.024 V

The MAX1444 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been
processed by all 10 stages. Each stage provides a
1-bit resolution.
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b). Switches S2a and S2b set the common
mode for the amplifier input. The resulting differential
Figure 1. Pipelined Architecture—Stage Blocks
V
IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED)
V
IN
IN
= INPUT VOLTAGE BETWEEN
V
IN
FLASH
ADC
1.5 BITS
STAGE 1
T/H
______________________________________________________________________________________
Input Track-and-Hold Circuit
DAC
MDAC
Detailed Description
DIGITAL ALIGNMENT LOGIC
Σ
STAGE 2
D9–D0
10
x2
10-Bit, 40Msps, 3.0V, Low-Power
V
OUT
STAGE 10
ADC with Internal Reference
voltage is held on C2a and C2b. Switches S4a, S4b,
S5a, S5b, S1, S2a, and S2b are then opened before
S3a, S3b, and S4c are closed, connecting capacitors
C1a and C1b to the amplifier output. This charges C1a
and C1b to the same values originally held on C2a and
C2b. This value is then presented to the first-stage
quantizer and isolates the pipeline from the fast-chang-
ing input. The wide-input-bandwidth T/H amplifier
allows the MAX1444 to track and sample/hold analog
inputs of high frequencies beyond Nyquist. The analog
inputs (IN+ and IN-) can be driven either differentially
or single-ended. It is recommended to match the
impedance of IN+ and IN- and set the common-mode
voltage to midsupply (V
The MAX1444 full-scale range is determined by the
internally generated voltage difference between REFP
(V
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (V
are internally buffered, low-impedance outputs.
Figure 2. Internal T/H Circuit
Analog Input and Reference Configuration
DD
IN+
IN-
/2 + V
TRACK
S4a
S4b
REFIN
HOLD
/4) and REFN (V
S4c
TRACK
HOLD
C2a
C2b
DD
INTERNAL
S2a
INTERNAL
/2) for optimum performance.
BIAS
BIAS
CLK
S1
INTERNAL
NON-OVERLAPPING
CLOCK SIGNALS
S2b
DD
C1a
C1b
/2 - V
DD
COM
COM
/2), and REFN
S5a
S5b
REFIN
S3a
S3b
/4). The
OUT
OUT
11