MAX1084BCSA Maxim Integrated, MAX1084BCSA Datasheet - Page 8

• Manufacturer Part Number: MAX1084BCSA
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1084BCSA

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended
• Snr: 60 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOIC-8 Narrow
• Maximum Power Dissipation: 471 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
The MAX1084/MAX1085 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 10-bit output.
Figure 3 shows the MAX1084/MAX1085 in their simplest
configuration. The internal reference is trimmed to 2.5V.
The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1084/MAX1085 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current to 2µA (typ); pulling SHDN high
puts the device into operational mode. Pulling CS low ini-
tiates a conversion that is driven by SCLK. The conver-
sion result is available at DOUT in unipolar serial format.
The serial data stream consists of three zeros, followed
by the data bits (MSB first). All transitions on DOUT
occur 20ns after the rising edge of SCLK. Figures 8 and
9 show the interface timing information.
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
8
_______________Detailed Description
_______________________________________________________________________________________
a) HIGH-Z TO V
a) V
DOUT
DOUT
OH
TO HIGH-Z
OH
6kΩ
6kΩ
AND V
OL
TO V
DGND
DGND
OH
Converter Operation
C
C
LOAD
LOAD
= 20pF
= 20pF
Figure 4 shows the sampling architecture of the ADC’s
comparator. The full-scale input voltage is set by the
internal reference (V
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor C
interval. At this instant, the T/H switches the input side
of C
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from C
HOLD
b) HIGH-Z TO V
to GND. The retained charge on C
b) V
HOLD
OL
HOLD
DOUT
DOUT
TO HIGH-Z
. Bringing CS low ends the acquisition
OL
AND V
REF
to the binary-weighted capacitive
OH
= +2.5V).
TO V
V
V
DD
DD
OL
6kΩ
6kΩ
C
C
LOAD
DGND
DGND
LOAD
= 20pF
= 20pF
Analog Input
HOLD
Track/Hold
repre-