MAX1136EUA Maxim Integrated, MAX1136EUA Datasheet - Page 13

• Manufacturer Part Number: MAX1136EUA
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1136EUA

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-8
• Maximum Power Dissipation: 362 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V

A write cycle begins with the bus master issuing a
START condition followed by seven address bits (Figure
7) and a write bit (R/W = 0). If the address byte is suc-
cessfully received, the MAX1136–MAX1139 (slave)
issues an acknowledge. The master then writes to the
slave. The slave recognizes the received byte as the
setup byte (Table 1) if the most significant bit (MSB) is
1. If the MSB is 0, the slave recognizes that byte as the
Figure 9. Write Cycle
Table 1. Setup Byte Format
(MSB)
BIT 7
REG
BIT
7
6
5
4
3
2
1
0
Configuration/Setup Bytes (Write Cycle)
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
______________________________________________________________________________________
BIP/UNI
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
NAME
BIT 6
SEL2
SEL2
SEL1
SEL0
REG
CLK
RST
X
A. ONE- BYTE WRITE CYCLE
B. TWO-BYTE WRITE CYCLE
S
S
1
1
SLAVE ADDRESS
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
Three bits select the reference voltage and the state of AIN_/REF (Table 6). Defaulted to 000 at
power-up.
1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.
1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up.
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t care, can be set to 1 or 0.
7
7
BIT 5
SEL1
SETUP OR CONFIGURATION BYTE
SETUP OR CONFIGURATION BYTE
MSB DETERMINES WHETHER
MSB DETERMINES WHETHER
W
W
1 1
1 1
A
A
CONFIGURATION BYTE
CONFIGURATION BYTE
BIT 4
SEL0
SETUP OR
SETUP OR
8
8
configuration byte (Table 2). The master can write either
one or two bytes to the slave in any order (setup byte
then configuration byte; configuration byte then setup
byte; setup byte or configuration byte only; Figure 9). If
the slave receives a byte successfully, it issues an
acknowledge. The master ends the write cycle by issu-
ing a STOP condition or a repeated START condition.
When operating in HS-mode, a STOP condition returns
the bus into F/S-mode (see the HS-Mode section).
A
A
1
1
BIT 3
CLK
P or Sr
CONFIGURATION BYTE
1
DESCRIPTION
SETUP OR
8
NUMBER OF BITS
BIP/UNI
BIT 2
A
1
P or Sr
1
NUMBER OF BITS
BIT 1
RST
(LSB)
BIT 0
X
13