MAX1134BEAP-T Maxim Integrated, MAX1134BEAP-T Datasheet - Page 7

• Manufacturer Part Number: MAX1134BEAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1134BEAP-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 150 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 83 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 3.135 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.2 V

PIN
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
SSTRB
NAME
DGND
DGND
AGND
SHDN
AGND
DOUT
AV
AV
SCLK
DV
CREF
REF
RST
DIN
AIN
CS
P2
P1
P0
DD
DD
DD
16-Bit ADCs, 150ksps, 3.3V Single Supply
_______________________________________________________________________________________
ADC Reference Input. Connect a 2.048V voltage source to REF. Bypass REF to AGND with a 4.7µF capacitor.
Analog Supply. Connect to pin 4.
Analog Ground. This is the primary analog ground (star ground).
Analog Supply, 3.3V ±5%. Bypass AV
Digital Ground
Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
User-Programmable Output 2
User-Programmable Output 1
User-Programmable Output 0
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before
the MSB decision. It is high impedance when CS is high in external clock mode.
Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.
Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section.
Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated
on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed.
Digital Ground. Connect to pin 5.
Digital Supply, 3.3V ±5%. Bypass DV
Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.
Chip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high impedance. In
external clock mode, SSTRB is high impedance when CS is high.
Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with a 1µF capacitor.
Analog Ground. Connect to pin 3.
Analog Input
DD
DD
to DGND (pin 14) with a 0.1µF capacitor.
to AGND (pin 3) with a 0.1µF capacitor.
FUNCTION
Pin Description
7