MAX1133BEAP Maxim Integrated, MAX1133BEAP Datasheet - Page 11

• Manufacturer Part Number: MAX1133BEAP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1133BEAP

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 92 dB
• Interface Type: Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal or External

Figure 3. Long Acquisition Mode (32-Clock Cycles) External Clock, Bipolar Mode
low for a maximum of 6µs, during which time SCLK
should remain low for best noise performance. An inter-
nal register stores data when the conversion is in
progress. SCLK clocks the data out of the internal stor-
age register at any time after the conversion is com-
plete.
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 15 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 4). CS does not need to be held low
once a conversion is started.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Figure 5 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in to
the MAX1132/MAX1133 at clock rates up to 4.8MHz,
provided that the minimum acquisition time, t
kept above 1.14µs in bipolar mode and 1.82µs in
unipolar mode. Data can be clocked out at 8MHz.
The output data format is straight binary for unipolar
conversions and two’s complement in bipolar mode. In
both modes the MSB is shifted out of the MAX1132/
MAX1133 first.
The falling edge of CS does NOT start a conversion on
the MAX1132/MAX1133. The first logic high clocked into
DIN is interpreted as a start bit and defines the first bit of
the Control Byte. A conversion starts on the falling edge
of SCLK, after the seventh bit of the Control Byte (the P1
bit) is clocked into DIN. The start bit is defined as:
SSTRB
DOUT
SCLK
DIN
STATE
CS
A/D
START
IDLE
1
UNI/
BIP
______________________________________________________________________________________
INT/
EXT
16-Bit ADC, 200ksps, 5V Single-Supply
t
ACQ
M1
4
M0
ACQUISITION
P2
Data Framing
P1
Output Data
P0
8
ACQ
, is
15
When power is first applied to the MAX1132/MAX1133
or if RST is pulsed low, the internal calibration registers
are set to their default values. The user-programmable
registers (P0, P1, and P2) are low, and the device is
configured for bipolar mode with internal clocking.
To compensate the MAX1132/MAX1133 for temperature
drift and other variations, they should be periodically
calibrated. After any change in ambient temperature
more than 10°C the device should be recalibrated. A
100mV change in supply voltage or any change in the
reference voltage should be followed by a calibration.
Calibration corrects for errors in gain, offset, integral
nonlinearity, and differential nonlinearity. The MAX1132/
MAX1133 should be calibrated after power-up or the
assertion of reset. Make sure the power supplies and
the reference voltage have fully settled prior to initiating
the calibration sequence.
Initiate calibration by setting M1 = 0 and M0 = 1 in the
Control-Byte. In internal clock mode, SSTRB goes low at
MSB
B15
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g., after AV
applied, or as the first high bit clocked into DIN
after CS is pulsed high, then low.
If a falling edge on CS forces a start bit before the
conversion or calibration is complete, then the
current operation will be terminated and a new
one started.
B14
B13
19
CONVERSION
Applications Information
B4
with Reference
B3
29
B2
OR
B1
LSB
B0
Power-On Reset
32
FILLED WITH
ZEROS
Calibration
IDLE
DD
11
is