MAX1286EKA-T Maxim Integrated, MAX1286EKA-T Datasheet - Page 12

• Manufacturer Part Number: MAX1286EKA-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1286EKA-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 150 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: 3-Wire, Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Maximum Power Dissipation: 696 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: External

For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
12
CNVST
SMP
CKE
R/W
SCLK
D/A
DOUT
UA
BF
CONTROL BIT
______________________________________________________________________________________
P
S
QSPI
Layout, Grounding, and Bypassing
MISO
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
MSB
SCK
B11
CS
SS
SAMPLING INSTANT
1
B10
MAX1286–MAX1289
V
DD
B9
SETTINGS
1
X
X
X
X
X
X
0
B8
1ST BYTE READ
4
CNVST
SCLK
DOUT
MAX1286–
MAX1289
B7
SPI Data Input Sample Phase. Input data is sampled at the middle of the data
output time.
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial
clock.
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer Full Status Bit
B6
B5
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
B4
8
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (V
degrade the performance of the ADC’s fast comparator.
Bypass V
located as close as possible to the MAX1286–MAX1289s’
power-supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
B3
B2
DD
to the star ground with a 0.1µF capacitor,
B1
LSB
B0
2ND BYTE READ
12
HIGH-Z
16
DD
) may