MAX192AEWP/GG8 Maxim Integrated, MAX192AEWP/GG8 Datasheet - Page 7

• Manufacturer Part Number: MAX192AEWP/GG8
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX192AEWP/GG8

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 640 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 3. Block Diagram
The MAX192 uses a successive-approximation conver-
sion technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX192.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer
to Tables 1 and 2 to configure the channels.
In differential mode, IN- and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
REFADJ
SHDN
AGND
AGND
SCLK
VREF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
DIN
CS
18
19
17
10
13
12
11
1
2
3
4
5
6
7
8
9
REGISTER
ANALOG
INPUT
SHIFT
INPUT
MUX
REFERENCE
+2.46V
_______________________________________________________________________________________
CONTROL
T/H
LOGIC
Detailed Description
Pseudo-Differential Input
20k
A
+4.096V
IN
CLOCK
1.65
CLOCK
SAR
ADC
INT
REF
OUT
MAX192
REGISTER
OUTPUT
SHIFT
14
20
15
16
DOUT
SSTRB
V
DGND
DD
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- (the select-
ed analog input, respectively) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). In single-ended mode, IN- is
simply AGND. This unbalances node ZERO at the input
of the comparator. The capacitive DAC adjusts during
the remainder of the conversion cycle to restore its
node ZERO to 0V within the limits of its resolution. This
action is equivalent to transferring a charge of
16pF x (V
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Figure 4. Equivalent Input Circuit
Low-Power, 8-Channel,
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.
DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF
HOLD
AGND
CH0
CH1
CH2
CH3
CH6
CH4
CH5
CH7
VREF
IN
as a sample of the signal at IN+.
+ - V
INPUT
Serial 10-Bit ADC
MUX
HOLD
IN
C
-) from C
CAPACITIVE DAC
SWITCH
–
from the positive input (IN+) to the
C
16pF
HOLD
TRACK
SWITCH
+
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
T/H
HOLD
10k
R
S
HOLD
ZERO
to the binary-weighted
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
HOLD
. The
7