MAX146BEAP/GH9 Maxim Integrated, MAX146BEAP/GH9 Datasheet - Page 12

• Manufacturer Part Number: MAX146BEAP/GH9
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX146BEAP/GH9

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Number Of Converters: 1
• Voltage Reference: Internal 2.5 V or External

+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX146/MAX147’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX146/MAX147 are compatible with SPI™/
QSPI™ and Microwire™ devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time. Using the Typical Operating
Circuit, the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 12-bit conversion result). See Figure
20 for MAX146/MAX147 QSPI connections.
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
Figure 6. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f
12
1) Set up the control byte for external clock mode and
2) Use a general-purpose I/O line on the CPU to pull
3) Transmit TB1 and, simultaneously, receive a byte
SSTRB
DOUT
SCLK
A/D STATE
DIN
CS
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
CS low.
and call it RB1. Ignore RB1.
______________________________________________________________________________________
START
1
SEL2 SEL1 SEL0
IDLE
How to Start a Conversion
RB1
4
UNI/
BIP
Simple Software Interface
SGL/
(f
DIF
ACQUISITION
SCLK
1.5µs
t
ACQ
PD1
= 2MHz)
PD0
8
MSB
B11
B10
B9
12
RB2
B8
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is two’s
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
The MAX146/MAX147 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX146/MAX147. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
5) Transmit a byte of all zeros ($00 hex) and, simulta-
6) Pull CS high.
CONVERSION
B7
neously, receive byte RB2.
neously, receive byte RB3.
B6
B5
16
B4
B3
B2
B1
20
RB3
LSB
B0
FILLED WITH
ZEROS
IDLE
Clock Modes
Digital Output
SCLK
24
≤ 2MHz)