MAX1415EUE Maxim Integrated, MAX1415EUE Datasheet - Page 22

• Manufacturer Part Number: MAX1415EUE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1415EUE

• Number Of Channels: 2
• Architecture: Sigma-Delta
• Conversion Rate: 0.5 KSPs
• Resolution: 16 bit
• Input Type: Differential
• Snr: No
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-16
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: - 45 C
• Number Of Converters: 1
• Voltage Reference: 1.75 V

The MAX1415/MAX1416 perform analog-to-digital con-
versions using a single-bit, 2nd-order, switched-capac-
itor, sigma-delta modulator. The sigma-delta modulator
converts the input signal into a digital pulse train whose
average duty cycle represents the digitized signal infor-
mation. A single comparator within the modulator quan-
tizes the input signal at a much higher sample rate than
the bandwidth of the input.
The MAX1415/MAX1416 modulator provides 2nd-order
frequency shaping of the quantization noise resulting
from the single-bit quantizer. The modulator is fully dif-
ferential for maximum signal-to-noise ratio and mini-
mum susceptibility to power-supply and common-mode
noise. A single-bit data stream is then presented to the
digital filter for processing to remove the frequency-
shaped quantization noise.
The modulator sampling frequency is f
regardless of gain, where f
frequency of the signal at CLKIN.
The MAX1415/MAX1416 contain an on-chip, digital low-
pass filter that processes the 1-bit data stream from the
modulator using a SINC
filter has a settling time of three output data periods.
Figure 6 shows the filter frequency response. The
SINC
times the first notch frequency. This results in a cutoff
frequency of 15.72Hz for a first filter notch frequency of
60Hz (output data rate of 60Hz). The response shown
in Figure 5 is repeated at either side of the digital filter’s
sample frequency, f
data rate), and at either side of the related harmonics
(2f
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Figure 6. Frequency Response of the SINC
60Hz)
22
M
, 3f
______________________________________________________________________________________
3
M
characteristic -3dB cutoff frequency is 0.262
, and so on).
-100
-120
-140
-160
-20
-40
-60
-80
0
0
20
M
40 60 80
(f
3
M
(sinx/x)
FREQUENCY (Hz)
= 19.2kHz for 60Hz output
CLKIN
100 120 140 160 180 200
f
CLK = 1
FS1 = 0
FS0 = 1
f
CLKIN
N
3
Filter Characteristics
= 60Hz
response. The SINC
(CLKDIV = 0) is the
Digital Filtering
= 2.4576MHz
3
Filter (Notch at
Modulator
CLKIN
/ 128,
3
The output data rate for the digital filter corresponds with
the positioning of the first notch of the filter’s frequency
response. Therefore, for the plot in Figure 6, where the first
notch of the filter is 60Hz, the output data rate is 60Hz. The
notches of the SINC
first notch frequency. The SINC
tion of better than 100dB at these notches.
Determine the cutoff frequency of the digital filter by load-
ing the appropriate values into the CLK, FS0, and FS1
bits in the clock register (see
different cutoff frequency with FS0 and FS1 changes the
frequency of the notches, but it does not alter the profile
of the frequency response.
For step changes at the input, allow a settling time
before valid data is read. The settling time depends on
the output data rate chosen for the filter. The worst-
case settling time of a SINC
input is four times the output data period. By synchro-
nizing the step input using FSYNC, the settling time
reduces to three times the output data period. If FSYNC
is high during the step input, the filter settles in three
times the data output period after FSYNC falls low.
The digital filter does not provide any rejection close to
the harmonics of the modulator sample frequency. Due to
the high oversampling ratio of the MAX1415/MAX1416,
these bands occupy only a small fraction of the spectrum
and most broadband noise is filtered. The analog filtering
requirements in front of the MAX1415/MAX1416 are
reduced compared to a conventional converter with no
on-chip filtering. In addition, the devices provide excellent
common-mode rejection to reduce the common-mode
noise susceptibility.
Additional filtering prior to the MAX1415/MAX1416 elim-
inates unwanted frequencies the digital filter does not
reject. Use additional filtering to ensure that differential
noise signals outside the frequency band of interest do
not saturate the analog modulator.
If passive components are in the path of the analog
inputs when the device is in unbuffered mode, ensure
the source impedance is low enough (Figure 2) not to
introduce gain errors in the system. This significantly
limits the amount of passive anti-aliasing filtering that
can be applied in front of the MAX1415/MAX1416 in
unbuffered mode. In buffered mode, large source
impedance causes a small DC-offset error, which can
be removed by calibration.
3
filter are repeated at multiples of the
3
Table 13). Programming a
3
filter for a full-scale step
filter provides an attenua-
Analog Filtering