MAX1065BEUI Maxim Integrated, MAX1065BEUI Datasheet - Page 8

• Manufacturer Part Number: MAX1065BEUI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1065BEUI

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 165 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 1026 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1065/MAX1066 use a successive-approximation
(SAR) conversion technique with an inherent track-and-
hold (T/H) stage to convert an analog input into a 14-bit
digital output. Parallel outputs provide a high-speed inter-
face to most microprocessors (µPs). The Functional
Diagram shows a simplified internal architecture of the
MAX1065/MAX1066. Figure 3 shows a typical application
circuit for the MAX1066.
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13
Delay Time and Bus Relinquish Time
Figure 2. MAX1065/MAX1066 Timing Diagram
8
D0–D13
_______________________________________________________________________________________
1mA
a) HIGH-Z TO V
DGND
V
V
OL
OH
TO V
TO HIGH-Z
D7/D13–D0/D8*
OH,
OH,
AND
D0–D13
HBEN*
C
EOC
LOAD
R/C
Detailed Description
CS
*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.
= 20pF
Converter Operation
t
t
DH
HI–Z
CSL
b) HIGH-Z TO V
D0–D13
V
V
OH
OL
TO V
TO HIGH-Z
1mA
t
ACQ
OL,
t
CSH
DV
AND
OL,
DD
C
DGND
t
DS
LOAD
REF POWER-
DOWN BIT
= 20pF
t
CONV
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent track-and-hold function. The sin-
gle-ended input is connected between AIN and AGND.
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Internal protection diodes, which clamp the analog
input to AV
from AGND - 0.3V to AV
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
t
DV
t
DO
BYTE VALID
HIGH/LOW
DD
and/or AGND, allow the input to swing
DATA VALID
t
DO1
BYTE VALID
HIGH/LOW
DD
t
t
t
EOC
BR
BR
Track and Hold (T/H)
+ 0.3V, without damaging
HI-Z
Input Bandwidth
Analog Input