MAX1137EUA-T Maxim Integrated, MAX1137EUA-T Datasheet - Page 5

• Manufacturer Part Number: MAX1137EUA-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1137EUA-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 362 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V

TIMING CHARACTERISTICS (Figure 1) (continued)
(V
4.096V (MAX1136/MAX1138), f
Tables 1–5 for programming notation.).)
Note 1: For DC accuracy, the MAX1136/MAX1138 are tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV
Note 9: Measured as for the MAX1137/MAX1139
Note 10: A master device must provide a data hold time for SDA (referred to V
Note 13: f
Note 11: The minimum value is specified at +25°C.
Note 12: C
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal after
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
DD
= 2.7V to 3.6V (MAX1137/MAX1139), V
devices are configured for unipolar, single-ended inputs.
offsets have been calibrated.
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit ).
and for the MAX1136/MAX1138
SCL’s falling edge (see Figure 1).
SCL
PARAMETER
⎡
⎢
⎣
B
⎡
⎢
⎣
[
[
V
= total capacitance of one bus line in pF.
V
FS
FS
must meet the minimum clock low time plus the rise/fall times.
( .
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
( .
5 5
3 6
V
_______________________________________________________________________________________
V
( .
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
( .
5 5
)
3 6
)
−
−
V
V
V
V
FS
FS
−
−
( .
( .
4 5
2 7
4 5
2 7
.
.
SCL
V
V
V
V
)
)
)
)
]
= 1.7MHz, T
]
×
×
SYMBOL
t
SU
2
2
V
t
V
t
t
RCL1
t
t
N
RDA
N
REF
RCL
FCL
FDA
C
t
REF
,
SP
−
B
−
STO
1
1
⎤
⎥
⎦
⎤
⎥
⎦
DD
A
= 4.5V to 5.5V (MAX1136/MAX1138), V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
(Notes 10 and 13)
= T
MIN
to T
MAX
CONDITIONS
DD
, unless otherwise noted. Typical values are at T
DD
DD
DD
DD
DD
= 5V and the MAX1137/MAX1139 are tested at V
to 0.7V
to 0.7V
to 0.7V
to 0.7V
to 0.7V
IL
DD
DD
DD
DD
DD
of SCL) in order to bridge the undefined region of
(Note 11)
P-P
.
REF
= 2.048V (MAX1137/MAX1139), V
DD
.
MIN
160
20
20
20
20
20
0
TYP
A
MAX
160
160
160
400
80
80
10
DD
= +25°C. See
= 3V. All
UNITS
REF
pF
ns
ns
ns
ns
ns
ns
ns
5
=