MAX1143BCAP Maxim Integrated, MAX1143BCAP Datasheet - Page 11

• Manufacturer Part Number: MAX1143BCAP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1143BCAP

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 82 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

In external clock mode, SSTRB is high-impedance
when CS is high. In external clock mode, CS is normally
held low during the entire conversion. If CS goes high
during the conversion, SCLK is ignored until CS goes
low. This allows external clock mode to be used with 8-
bit bytes.
In internal clock mode, the MAX1142/MAX1143 gener-
ates its own conversion clock. This frees the micro-
processor from the burden of running the SAR conver-
sion clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
up to 8MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB will be
low for a maximum of 6µs, during which time SCLK
should remain low for best noise performance. An inter-
nal register stores data when the conversion is in
progress. SCLK clocks the data out of the internal stor-
age register at any time after the conversion is com-
plete.
Table 2. User-Programmable Outputs
Figure 2. Short Acquisition Mode (24-Clock Cycles) External Clock, Bipolar Mode
OUTPUT
SSTRB
DOUT
PIN
SCLK
P2
P1
P0
DIN
STATE
CS
A/D
START
IDLE
PROGRAMMED
1
CONTROL-
THROUGH
UNI/
BIP
______________________________________________________________________________________
BYTE
14-Bit ADC, 200ksps, +5V Single-Supply
Bit 2
Bit 1
Bit 0
INT/
EXT
ACQUISITION
t
ACQ
M1
4
M0
POWER-ON
DEFAULT
P2
OR RST
0
0
0
P1
Internal Clock
P0
8
MSB
B13
U ser p r og r am m ab l e outp uts fol l ow the state of the C ontr ol - Byte’ s thr ee LS Bs,
and ar e up d ated si m ul taneousl y w hen a new C ontr ol - Byte i s w r i tten. O utp uts
ar e p ush- p ul l . In har d w ar e and softw ar e shutd ow n, these outp uts ar e
unchang ed and r em ai n l ow - i m p ed ance.
B12
B11
B10
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 15 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 4). CS does not need to be held low
once a conversion is started.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Figure 5 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted into
the MAX1142/MAX1143 at clock rates up to 4.8MHz,
provided that the minimum acquisition time,
t
in unipolar-mode. Data can be clocked out at 8MHz.
The output data format is straight binary for unipolar
conversions and two’s complement in bipolar mode. In
both modes the MSB is shifted out of the MAX1142/
MAX1143 first.
12
ACQ
B9
, is kept above 1.14µs in bipolar mode and 1.82µs
CONVERSION
B8
B7
15
DESCRIPTION
with Reference
B2
B1
21
LSB
B0
X
X
24
Output Data
FILLED WITH
ZEROS
IDLE
11