MAX1109EUB-T Maxim Integrated, MAX1109EUB-T Datasheet - Page 16

• Manufacturer Part Number: MAX1109EUB-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1109EUB-T

• Number Of Channels: 2
• Architecture: SAR
• Conversion Rate: 50 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 49 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 444 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
to the SCLK pin; varying the analog input alters the
result of conversion that is clocked out at the DOUT pin.
A total of 10 clock cycles is required per conversion.
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte.
Acquisition starts on the falling edge of the fourth SCLK
and lasts for two SCLKs in external clock mode or four
SCLKs in internal clock mode. Conversion starts imme-
diately after acquisition is completed. The start bit is
defined as:
Figure 10. Continuous Conversion, External Clock Mode, 10 Clocks/Conversion Timing
Figure 11. Continuous Conversion, External Clock Mode, 16 Clocks/Conversion Timing
16
______________________________________________________________________________________
The first high bit clocked into DIN with CS
low any time the converter is idle; e.g., after
V
DD
DOUT
SCLK
A/D STATE
DIN
DOUT
SCLK
CS
is applied.
DIN
CS
S
1
S
IDLE
1
CONTROL BYTE 0
CONTROL BYTE 0
OR
t
ACQ
Data Framing
8
8
D7
D7
CONVERSION RESULT 0
t
CONV
10 1
CONVERSION RESULT 0
D5
S
CONTROL BYTE 1
t
D0
ACQ
D0
The MAX1108/MAX1109 can run at a maximum speed
of 10 clocks per conversion. Figure 10 shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
Many microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion is
typically the fastest that a microcontroller can drive the
MAX1108/MAX1109. Figure 11 shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
S
17
In external clock mode, the first high bit
clocked into DIN after the bit 5 (D5) of a con-
version in progress is clocked onto the
DOUT pin.
In internal clock mode, the first high bit
clocked into DIN after the bit 4 (D4) is
clocked onto the DOUT pin.
CONTROL BYTE 1
D7
t
CONV
10 1
CONVERSION RESULT 1
D5
S
CONTROL BYTE 2
D7
25
t
ACQ
OR
D0
CONVERSION RESULT 1
t
CONV
D7
10 1
S
D0
S