MAX1168BCEG Maxim Integrated, MAX1168BCEG Datasheet - Page 16

• Manufacturer Part Number: MAX1168BCEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1168BCEG

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 88.5 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 762 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Table 5 shows the MAX1167/MAX1168 power-down
modes. Three internal reference modes and one exter-
nal reference mode are available. Select power-down
modes by writing to bits 2 and 1 in the command/con-
figuration/control register. The MAX1167/MAX1168
enter the selected power-down mode on the rising
edge of CS.
The internal reference stays on when CS is pulled high,
if bits 2 and 1 are set to zero. This mode allows for the
fastest turn-on time.
Setting bit 2 = 0 and bit 1 = 1 turns both the reference
and reference buffer off when CS is brought high. This
mode achieves the lowest supply current. The refer-
ence and buffer wake up on the falling edge of CS
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
Figure 8. Detailed SPI Interface Timing
Figure 9. Shutdown Sequence
16
DOUT
CS
______________________________________________________________________________________
DOUT
SCLK
COMPLETE CONVERSION SEQUENCE
DIN
CS
CONVERSION 0
POWERED UP POWERED DOWN
t
CSW
t
DV
t
CSS
t
DS
Power-Down Modes
t
DH
CONVERSION 1
POWERED UP
t
CL
t
CH
• • •
when in SPI/QSPI/MICROWIRE mode and on the falling
edge of DSPR when in DSP mode. Allow 5ms for the
internal reference to rise and settle when powering up
from a complete shutdown (V
The internal reference stays on and the buffer is shut off
on the rising edge of CS when bit 2 = 1 and bit 1 = 0.
The MAX1167/MAX1168 enter this mode on the rising
edge of CS. The buffer wakes up on the falling edge of
CS when in SPI/QSPI/MICROWIRE mode and on the ris-
ing edge of DSPR when in DSP mode. Allow 5ms for
V
down (V
to +4.096V in this mode.
Set both bit 2 and bit 1 to 1 to turn off the reference and
reference buffer to allow connection of an external ref-
erence. Using an external reference requires no extra
wake-up time.
Force DSPR high and DSEL low (MAX1168) for SPI/
QSPI/MICROWIRE interface mode. The falling edge of
CS wakes the analog circuitry and allows SCLK to clock
in data. Ensure the duty cycle on SCLK is between 45%
and 55% when operating at 4.8MHz (the maximum
clock frequency). For lower clock frequencies, ensure
the minimum high and low times are at least 93ns.
External-clock-mode conversions with
REF
to settle when powering up from a complete shut-
External Clock 8-Bit-Wide Data-Transfer Mode
REF
= 0, C
t
CP
t
DO
REF
= 1µF). V
t
(MAX1167 and MAX1168)
REF
CSH
REFCAP
= 0, C
Operating Modes
t
TR
REF
is always equal
= 1µF).