MAX1112EAP-T Maxim Integrated, MAX1112EAP-T Datasheet - Page 13

• Manufacturer Part Number: MAX1112EAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1112EAP-T

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 50 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V or External

In unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs, the output is two’s-com-
plement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format.
The MAX1112/MAX1113 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the devices. Bit
PD0 of the control byte programs the clock mode.
Figures 8–11 show the timing characteristics common
to both modes.
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
Figure 8. Detailed Serial-Interface Timing
Figure 9. External Clock Mode SSTRB Detailed Timing
SSTRB
SCLK
CS
SCLK
DOUT
DIN
CS
______________________________________________________________________________________
t
t
t
DV
SDV
CSS
t
DS
• • • •
t
• • •
• • •
DH
Clock Modes
t
DO
External Clock
+5V, Low-Power, Multi-Channel,
Digital Output
t
PD0 CLOCKED IN
CL
t
CH
• • •
• • •
• • •
t
• • •
SSTRB
conversion steps. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successive-
approximation bit decisions are made and appear at
DOUT on each of the next eight SCLK falling edges
(Figure 7). After the eight data bits are clocked out,
subsequent clock pulses clock out zeros from the
DOUT pin.
SSTRB and DOUT go into a high-impedance state
when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 9 shows the SSTRB
timing in external clock mode.
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors can degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
Serial 8-Bit ADCs
t
DO
• • •
• • •
• • • •
t
CSH
t
SSTRB
t
TR
t
STR
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