MAX1363EUB Maxim Integrated, MAX1363EUB Datasheet - Page 20

• Manufacturer Part Number: MAX1363EUB
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1363EUB

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C, Serial
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: uMAX
• Maximum Power Dissipation: 444.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
Select readback mode by setting CS3, CS2 to [1,1] in
the configuration byte. Begin a read operation to start
reading back monitor-setup data. Clock out delay bit
settings, INT_EN bit, and the lower and upper thresh-
olds programmed for each channel. Readback mode
follows exactly the same format as writing to the moni-
tor-setup data, with the exception of the first 4 alarm-
reset bits, which are always 1 (Table 13).
Reading in monitor mode reads back the alarm-status
register, latched-fault register, and current-conversion
results as shown in Table 14.
The MAX1363/MAX1364 register pointer loops back to
the beginning of the current-conversion result after
reading the last conversion result. Stop reading at any
time by asserting a STOP condition or NACK.
Note: The MAX1363/MAX1364 do not update the cur-
rent-conversion results register while reading in monitor
mode. Monitor mode resumes after a STOP condition
or NACK.
Table 13. Readback-Mode Format
Table 14. Reading in Monitor-Mode Data Format
Table 15. Alarm-Status Register
0 = Not-alarm condition.
1 = Alarm condition.
Table 16. Latched-Fault and Current-
Conversion Register
20
1
ALARM-STATUS REGISTER
ALARM RESET/SCAN SPEED
16-bit read
CH0 UP
AIN0
______________________________________________________________________________________
1
0/1
1
8 bits
1 D2 D1 D0 INT
16-bit read
CH0 LOW
AIN1
0/1
Reading in Monitor Mode
16-bit read
THRESHOLDS
CH1 UP
AIN2
24 bits
Readback Mode
0/1
AIN0
LATCHED-FAULT REGISTER
16, 32, 48, or 64 bits
16-bit read
MODE OR CS1, CS0 < 1)
(SKIP IF DIFFERENTIAL
CH1 LOW
AIN3
AIN1 THRESHOLDS
0/1
24 bits
The latched-fault register records a snapshot of the
alarming channel at the instance that a fault condition is
asserted. An alarm-status bit of 1 (Table 15) indicates a
fault, and the data in the latched-fault register of the
corresponding channel contains the conversion result
that caused the alarm to trip. Resetting alarms does not
clear the latched-fault register, thus the latched-fault
register contains valid data only if an alarm status bit is
high for the given channel.
The current-conversion register contains the most
recent conversion results. If the user attempts to read
past the last result of the current-conversion register,
the MAX1363/MAX1364 wraps back to the beginning of
the current-conversion result.
The latched-fault register and current-conversion regis-
ter follow the data format in the Reading a Conversion
( Read Cycle) section. Register length depends on the
number of conversions in one monitoring sequence.
For example, when channel pairs 0/1 and channels 2/3
are monitored differentially, there are only two conver-
sion results to report. The latched-fault register is 2 x 16
bits long, after which two current-conversion results fol-
low. Likewise, if CS0 and CS1 limit the upper bound of
the channel scan range from CH0 to CH2 in single-
ended mode, the latched-fault register clocks out 3 x
16 bits of data followed by the current-conversion
results, also 3 x 16 bits.
CH2 UP
Alarm-Status Register and Latched-Fault Register
0/1
(SKIP IF CS1, CS0 < 2)
AIN2 THRESHOLDS
CH2 LOW
24 bits
CURRENT-CONVERSION RESULTS
0/1
16, 32, 48, or 64 bits
CH3 UP
MODE OR CS1, CS0 < 3)
(SKIP IF DIFFERENTIAL
0/1
AIN3 THRESHOLDS
24 bits
CH3 LOW
0/1