MAX1065CEUI Maxim Integrated, MAX1065CEUI Datasheet - Page 12

• Manufacturer Part Number: MAX1065CEUI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1065CEUI

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 165 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Power Dissipation: 1026 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

For best performance, use printed circuit boards. Do not
run analog and digital lines parallel to each other, and do
not lay out digital signal paths underneath the ADC pack-
age. Use separate analog and digital ground planes with
only one point connecting the two ground systems (ana-
log and digital) as close to the device as possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, then isolate the digital and ana-
log supply by connecting them with a low-value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the AV
supply. Bypass AV
parallel with a 1µF to 10µF low-ESR capacitor and the
smallest capacitor closest to the device. Keep capacitor
leads short to minimize stray inductance.
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1065/MAX1066
are measured using the end-point method.
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Aperture jitter is the sample-to-sample variation in the
time between samples. Aperture delay is the time
between the rising edge of the sampling clock and the
instant when the actual sample is taken.
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N-bits):
where N = 14 bits.
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
12
______________________________________________________________________________________
Layout, Grounding, and Bypassing
SNR = (6.02 x N + 1.76)dB
DD
to AGND with a 0.1µF capacitor in
Aperture Jitter and Delay
Differential Nonlinearity
Signal-to-Noise Ratio
Integral Nonlinearity
Definitions
DD
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
V
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
TRANSISTOR COUNT: 15,140
PROCESS: BiCMOS
5
are the 2nd- through 5th-order harmonics.
SINAD dB
THD
1
=
is the fundamental amplitude and V
(
20
×
)
=
log
ENOB
Signal-to-Noise Plus Distortion
Spurious-Free Dynamic Range
20
⎡
⎢
⎢
⎢
⎢
⎢
⎣
⎛
⎜
⎝
×
log
Total Harmonic Distortion
=
V
Effective Number of Bits
2
SINAD
⎡
⎢
⎣
2
(
Noise Distortion
+
6 02
V
Chip Information
.
3
2
−
V
Signal
1 76
+
1
+
.
V
4
2
RMS
+
V
5
2
)
RMS
⎞
⎟
⎠
2
⎤
⎥
⎥
⎥
⎥
⎥
⎦
through
⎤
⎥
⎦