MAX1109EUB Maxim Integrated, MAX1109EUB Datasheet - Page 10

• Manufacturer Part Number: MAX1109EUB
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1109EUB

• Number Of Channels: 2
• Architecture: SAR
• Conversion Rate: 50 KSPS
• Resolution: 8 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Maximum Power Dissipation: 444 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
Figure 1. Load Circuits for Enable Time
The MAX1108/MAX1109 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to an 8-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (µPs). No external hold capacitors are required. All
of the MAX1108/MAX1109 operating modes are soft-
ware-configurable: internal or external reference, inter-
nal or external conversion clock, single-ended unipolar
or pseudo-differential unipolar/bipolar conversion, and
power down (Table 1).
The input architecture of the ADCs is illustrated in the
equivalent-input circuit of Figure 4 and is composed of
the T/H, the input multiplexer, the input comparator, the
switched capacitor DAC, the reference, and the auto-
zero rail.
The analog-inputs configuration is determined by the
control-byte through the serial interface as shown in
Table 2 (see Modes of Operation section and Table 1).
The eight modes of operation include single-ended,
pseudo-differential, unipolar/bipolar, and a V
toring mode. During acquisition and conversion, only
one of the switches in Figure 4 is closed at any time.
The T/H enters its tracking mode on the falling clock
edge after bit 4 (SEL0) of the control byte has been
shifted in. It enters its hold mode on the falling edge
after the bit 2 (I/EREF) of the control byte has been
shifted in.
For example, If CH0 and COM are chosen (SEL2 =
SEL1 = SEL0 = 1) for conversion, CH0 is defined as the
sampled input (SI), and COM is defined as the refer-
ence input (RI). During acquisition mode, the CH0
switch and the T/H switch are closed, charging the
10
_______________Detailed Description
DOUT
a) High-Z to V
______________________________________________________________________________________
3k
OH
DGND
and V
OL
to V
OH
C
LOAD
b) High-Z to V
DOUT
Analog Inputs
V
DD
OL
and V
3k
C
DGND
LOAD
Track/Hold
OH
DD
to V
moni-
OL
Figure 2. Load Circuits for Disable Time
Figure 3. Typical Operating Circuit
Figure 4. Equivalent Input Circuit
ANALOG
INPUTS
V
DD
DOUT
COM
GND
GND
CH1
CH0
REF
1 F
/ 2
3k
a) V
CH1
CH0
REF
DGND
MAX1108
MAX1109
OH
to High-Z
CAPACITIVE DAC
C
HOLD
18pF
DOUT
SCLK
HOLD
COM
GND
DIN
V
CS
DD
C
0.1 F
LOAD
TRACK
R
6.5k
IN
DOUT
b) V
1 F
V
DD
OL
V
to High-Z
DD
MISO (SI)
V
I/O
SCK (SK)
MOSI (SO)
DD
COMPARATOR
3k
C
DGND
CPU
LOAD
V
AUTOZERO
SS
RAIL