93AA86C-I/SNG Microchip Technology, 93AA86C-I/SNG Datasheet - Page 11

• Manufacturer Part Number: 93AA86C-I/SNG
• Description: EEPROM 1024x16-2048x8 1.8V Lead Free Package
• Manufacturer: Microchip Technology

Specifications of 93AA86C-I/SNG

• Product Category: EEPROM
• Rohs: yes
• Memory Size: 16 Kbit
• Organization: 256 x 8
• Data Retention: 200 yr
• Maximum Clock Frequency: 3 MHz
• Maximum Operating Current: 3 mA
• Operating Supply Voltage: 1.8 V, 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: Microwire
• Minimum Operating Temperature: - 40 C
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 1.8 V

3.0
TABLE 3-1:
3.1
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI = 0), any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed. CLK and DI
then become don't care inputs waiting for a new Start
condition to be detected.
 2004 Microchip Technology Inc.
Name
ORG
CLK
V
V
CS
DO
PIN DESCRIPTIONS
PE
Chip Select (CS)
Serial Clock (CLK)
DI
CC
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
SS
CKL
PIN DESCRIPTIONS
). This gives the controlling master
MSOP/TSSOP
SOIC/PDIP/
1
2
3
4
5
6
7
8
CSL
) between
CKH
SOT-23
N/A
N/A
) and
5
4
3
1
2
6
Chip Select
Serial Clock
Data In
Data Out
Ground
Organization / 93XX86C
Program Enable
Power Supply
3.3
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (T
tive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum Chip Select
low time (T
been initiated.
The Status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
3.5
When the ORG pin is connected to V
(x16) memory organization is selected. When the ORG
pin is tied to V
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX86A devices are always x8 organization and
93XX86B devices are always x16 organization.
Note:
Data In (DI)
Data Out (DO)
Organization (ORG)
CSL
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
) and an erase or write operation has
SS
Function
or Logic LO, the (x8) memory
CC
DS21797D-page 11
PD
or Logic HI, the
after the posi-