MAX3394EETA+T Maxim Integrated Products, MAX3394EETA+T Datasheet - Page 9

• Manufacturer Part Number: MAX3394EETA+T
• Description: IC LVL XLTR LV 6MBPS 8-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3394EETA+T

• Logic Function: Translator, Bidirectional, 3-State
• Number Of Bits: 2
• Input Type: Logic
• Output Type: Logic
• Data Rate: 6Mbps
• Number Of Channels: 2
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 50ns
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TDFN Exposed Pad
• Supply Voltage: 1.65 V ~ 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Figure 3. Push-Pull Driving I/O V
Figure 4. Open-Drain Driving I/O V
capacitive isolation between I/O lines. When one or
both I/O lines are at a logic-low level, the gate-control
logic turns the pass-FET on. When the pass-FET is
active, I/O V
the logic-low signal to be expressed simultaneously on
both I/O lines.
The MAX3394E/MAX3395E/MAX3396E have internal
10kΩ (typ) pullup resistors from I/O V
to the respective supply voltages, allowing operation
with open-drain drivers. Internal slew-rate enhancement
circuitry accelerates logic-state transitions, maintaining
a fast data rate with a higher bus load capacitance.
Additionally, the 10mA current sink drivers permit the
use of smaller external pullup resistors.
C
IOVL
C
IOVL
Octal-Level Translators with Speed-Up Circuitry
L
I/O V
_ and I/O V
V
L
L_
I/O V
_______________________________________________________________________________________
V
L
L_
V
L
V
L
V
EN
CC
L
V
L
MAX3394E
MAX3395E
MAX3396E
CC_
_ are connected, allowing
EN
CC_
Test Circuit and Timing
MAX3394E
MAX3395E
MAX3396E
Test Circuit and Timing
L
V
V
CC
_ and I/O V
CC
V
V
CC
CC
I/O V
CC_
I/O V
50Ω
CC
CC_
V
CC
_
V
CC
V
GATE
Internal slew-rate enhancement circuitry accelerates
logic-state changes by turning on MOSFETs M
M
M
the Functional Diagram ). During logic-state changes,
speed-up MOSFETS are triggered by I/O line voltage
thresholds. MOSFETS M
high-to-low logic transitions. M
during low-to-high logic transitions. Slew-rate enhance-
ment allows a fast data rate despite large capacitive bus
loads, and permits larger external pullup resistors.
P2
N3
during low-to-high logic transitions, and MOSFETs
and M
50%
N4
Internal Slew-Rate Enhancement
10%
50%
t
I/OVCC-VL
during high-to-low logic transitions (see
t
I/OVCC-VL
t
RVL
10%
t
90%
50%
RVL
N3
I/O V
90%
50%
I/O V
50%
CC
and M
L
P1
t
50%
I/OVCC-VL
t
I/OVCC-VL
50%
and M
50%
N4
90%
t
FVL
90%
t
FVL
sink 10mA during
P2
10%
10%
source 15mA
I/O V
L
P1
and
9