LCMXO2-1200HC-5TG100IR1 Lattice, LCMXO2-1200HC-5TG100IR1 Datasheet - Page 21

• Manufacturer Part Number: LCMXO2-1200HC-5TG100IR1
• Description: FPGA - Field Programmable Gate Array 1280 LUTs 80 I/O 3.3V -5 Speed IND
• Manufacturer: Lattice

Specifications of LCMXO2-1200HC-5TG100IR1

• Rohs: yes
• Number Of I/os: 80
• Maximum Operating Frequency: 141.645 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 3.49 mA
• Factory Pack Quantity: 90

In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling
edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to
switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.
Figure 2-14 shows the output register block on the left, top and bottom edges.
Figure 2-14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)
Right Edge
The output register block on the right edge is a superset of the output register on left, top and bottom edges of the
device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right
edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the out-
put register block on other edges.
In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling
edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used
to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.
Figure 2-15 shows the output register block on the right edge.
SCLK
TD
D0
D1
D
Q
D/L Q
D
D/L Q
Q
2-17
Q0
Q1
MachXO2 Family Data Sheet
Tri-state path
Output path
TQ
Q
Architecture