IS25CQ032-JKLE-TR ISSI, IS25CQ032-JKLE-TR Datasheet
IS25CQ032-JKLE-TR
Specifications of IS25CQ032-JKLE-TR
Related parts for IS25CQ032-JKLE-TR
IS25CQ032-JKLE-TR Summary of contents
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... GENERAL DESCRIPTION The IS25CQ032 are 32 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad- output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power supply, ranging from 2 ...
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... CS# 7 SO(IO1) 8 16-Pin SOIC Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 Vcc CE (IO1) HOLD# (IO3) 3 WP# (IO2) SCK 4 GND ) SI (IO0 8-Pin WSON SCLK 16 15 SI(IO0 GND 9 WP#(IO2) IS25CQ032 8 Vcc 7 HOLD#(IO3) SCK (IO0 2 ...
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... Hold: Pause serial communication by the master device without resetting (IO3) the serial sequence. When the QE bit of Status Register-2 is set for “1”, the function is Serial Data Input & Output (for 4xI/O read mode) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 3 ...
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... BLOCK DIAGRAM WP# (IO2) SI (IO0) SO (IO1) HOLD# (IO3) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 4 ...
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... SPI MODES DESCRIPTION Multiple IS25CQ032 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) ...
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... The devices have two superset features that can be enabled through specific software instructions and the Configuration Register: 1. Configurable sector size: The memory array of IS25CQ032 is divided into uniform 4 KByte sectors or uniform 64 KByte blocks (a block consists of sixteen adjacent sectors). Table 1 illustrates the memory map of the devices. The Configuration Register controls how the memory is mapped ...
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... Sector Sector 127 64 Sector 128 : : : : 64 Sector 255 64 Sector 256 : : : : 64 Sector511 64 Sector 512 : : : : 64 Sector 1023 IS25CQ032 Size Address Range 4 000000h - 000FFFh 4 001000h - 001FFFh : : 4 00F000h - 00FFFFh 4 010000h - 010FFFh 4 011000h - 011FFFh : : 4 01F000h - 01FFFFh : : 070000h – 07FFFFh 4 080000h – 08FFFFh 0F0000h – 0FFFFFh 4 100000h – 10FFFFh ...
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... SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground. Bit 6 Bit 5 Bit 4 Bit 3 QE BP3 BP2 BP1 IS25CQ032 ), the bits of Status Register IL ), the Status Register IH Bit 2 Bit 1 Bit 0 BP0 WEL WIP ...
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... Quad output function enable Status Register Write Disable: (See Table 10 for details) Bit 7 SRWD "0" indicates the Status Register is not write-protected (default) "1" indicates the Status Register is write-protected Table 7. Block Write Protect Bits for IS25CQ032 Status Register Bits BP3 BP2 BP1 0 ...
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... IL Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 The IS25CQ032 also provides two software write protection features: a. Before the execution of any program, erase or write status register instruction, the Write Enable Latch (WEL) bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled first, the program, erase or write register instruction will be ignored ...
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... Read 65 bytes of Security area Raw HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25CQ032. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. Integrated Silicon Solution, Inc.- www.issi.com Rev ...
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... BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle Table 12. Product Identification Product Identification Manufacturer ID Device ID: IS25CQ032 Dummy Bytes Device ID1 IS25CQ032 time duration. If the RES1 Data First Byte Second Byte Device ID1 Device ID2 15h ...
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... Rev. A 2/1/2013 by the first Manufacturer ID (9Dh) and the Device ID (46h, in the case of the IS25CQ032), each bit shifted out during the falling edge of SCK. If CE# stays low after the last bit of the Device ID is shifted out, the Manufacturer ID and Device ID will loop until CE# is pulled high ...
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... ID (7Fh). The manufacture and device ID can be read continuously, alternating from one to the others. The instruction is completed by driving CE# high Data Out2 IS25CQ032 ... 3 - BYTE ADDRESS ... ...
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... ADDRESS will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh) ADDRESS will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 15 ...
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... WRITE ENABLE OPERATION The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit of the IS25CQ032 is reset to the write –protected state after power-up. The WEL bit must be write enabled before any write operation, including sector, block erase, chip Figure 6 ...
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... Figure 9. Write Status Register Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 instruction, which can be used to check the progress or completion of an operation by reading the WIP bit of Status Register. or “1”s into the non-volatile BP3, BP2, BP1, BP0 and SRWD bits ...
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... DEVICE OPERATION (CONTINUED) READ COMMAND (READ DATA) OPERATION The Read Data (READ) instruction is used to read memory data of a IS25CQ032 under normal mode running MHz. The READ instruction code is transmitted via the Sl line, followed by three address bytes (A23 - A0) of the first memory location to be read. A total of 24 address ...
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... FAST_READ instruction. The FAST_READ instruction is terminated by driving CE# high ( Fast Read Data instruction is issued while IH , during the an Erase, Program or Write cycle is in process (BUSY=1) CT the instruction is ignored and will not have any effects on the current cycle IS25CQ032 19 ...
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... BYTE ADDRESS DATA OUT IS25CQ032 ). If a FRDO ... ... DATA OUT ...
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... Mode Reset (FFh) command. In subsequent FRDIO execution, the command code is not input, saving timing cycles as described in Figure 16 FRDIO , during the instruction is issued while an Erase, Program or Write CT cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle IS25CQ032 ). IH 21 ...
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... DATA OUT IO1 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 DATA OUT IS25CQ032 ... 3 - BYTE ADDRESS MODE BITS ... ... 20 22 ...
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... FRQO instruction. FRQO instruction is terminated by driving CE# high (V instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle IS25CQ032 ...
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... BYTE ADDRESS DATA OUT 1 DATA OUT IS25CQ032 ... ... DATA OUT ...
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... The first bit (MSb) is output on IO3, while simultaneously the second bit is output on IO2, the Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 third bit is output on IO1, etc. Figure 18 illustrates the timing sequence. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out ...
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... DATA OUT 2 DATA OUT 3 DATA OUT IS25CQ032 BYTE ADDRESS MODE BITS ...
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... MODE BITS 4 Dummy Clock command after a system reset. The timing sequence is different depending whether the MR command is used after an FRDIO or FRQIO, as shown in Figure 20. IS25CQ032 DATA OUT 1 DATA OUT 2 27 ...
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... Figure 20, Mode Reset Command Mode Reset for CE SCK SIO INSTRUCTION = 1111 1111b HIGH IMPEDANCE SO Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 Quad I INSTRUCTION = 1111 1111b IS25CQ032 Mode Reset for Dual I ...
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... Figure 21. Page Program Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “ ...
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... IO2 IO3 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 BYTE ADDRESS 23 00110010b DATA IS25CQ032 ... ... 0 31 ...
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... BLOCK_ER COMMAND (BLOCK ERASE) OPERATION A Block Erase (BLOCK_ER) instruction erases a 64 Kbyte block of the IS25CQ032. Before the execution of a BLOCK_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation. ...
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... DEVICE OPERATION (CONTINUED) Figure 22. Sector Erase Sequence Figure 23. Block Erase Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 33 ...
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... Figure 24. Chip Erase Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 34 ...
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... The SIR protection bit is in the address 000040h Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 MSB Data Byte 2 IS25CQ032 ) is initiated. While the potp ... ... 24-bit address 42 43 ... ... 6 5 Data Byte n 35 ...
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... Byte1 Byte2 X X Bit 1~bit 7 do not care Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 Byte64 IS25CQ032 OTP control byte Byte65 Bit 0 When bit the 64 OTP bytes become read only 36 ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 th ) byte keeps being read on the SO pin ... ... MSB 24-bit address 46 47 ... ... Data output N Data output 2 IS25CQ032 Data Out0 0 37 ...
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... C to +125 o Standard Package 240 C 3 Seconds o Lead-free Package 260 C 3 Seconds -0 VCC + 0 VCC + 0 0.5 V. During voltage transitions, input or I/O pins may CC IS25CQ032 o C IS25CQ032 105 - - 105 - 125 C 2.70 V – ...
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... CE 3.60V, CE 130 2.1 mA 2.70V < V < 3.60V I = -100 µA OH IS25CQ032 Ty Min Max -0.5 0.3Vcc 0. 0 0.45 – 0 Units mA mA µA mA µA µA ...
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... EC Chip Erase Time (32Mb) t Page Program Time Set-up Time VCS CC t res1 Write Status Register time w Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 = -40°C to +125° Min Typ 500 ...
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... AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING Note: 1. For SPI Mode 0 (0,0) Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 (1) IS25CQ032 41 ...
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... AC CHARACTERISTICS (CONTINUED) HOLD TIMING PIN CAPACITANCE ( MHz 25°C ) Typ OUT Note: These parameters are characterized but not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 Max Units IS25CQ032 Conditions OUT 42 ...
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... OUTPUT TEST LOAD 30pF Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 43 ...
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... At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. All Write Commands are Rejected tVCE tPUW Parameter IS25CQ032 Read Access Allowed Device fully accessible Time Min. Max. Unit 10 us ...
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... From writing erase command to erase completion 1 2 From writing program command to program completion 8 25 Min Typ Unit 100,000 Cycles 20 Years 2,000 Volts 200 Volts 100 + I mA CC1 IS25CQ032 Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78 45 ...
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... PACKAGE TYPE INFORMATION (CONTINUED pin – SOIC 300mil body width, 16-lead Plastic Small Outline Package 10.1 10 1.27 0.33 0.51 Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 Millimeters 9 0.23 0.32 8 0.1 IS25CQ032 Detail A Detail A 0 1.27 8 0.1 0.3 46 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JB 8-Pin SOIC 208mil Broad Small Outline Integrated Circuit Package (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 47 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JF 8-Pin 208mil VSOP Package Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 48 ...
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... PACKAGE TYPE INFORMATION (CONTINUED) JK 8-Pin WSON Ultra-Thin Small Outline No-Lead Package (Unit: millimeters) Note: Package dimensions are shown in mm Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 49 ...
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... A0 through A11 are not decoded. The remaining sectors within the same block remain in read-only mode 26h A23-A16 IS25CQ032 Command Cycle 4 Bytes 1 Byte A15-A8 A7-A0 Maximum Frequency ...
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... Sector Unlock command. The instruction code does not require an address to be specified, as only Figure e. Sector Lock Sequence Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 one sector can be enabled at a time. The remaining sectors within the same block remain in read-only mode. 51 ...
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... Integrated Silicon Solution, Inc.- www.issi.com Rev. A 2/1/2013 IS25CQ032 52 ...
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... IS25CQ032-JBLE 8-pin SOIC 208mil IS25CQ032-JFLE 8-pin VSOP 208mil IS25CQ032-JKLE 8-pin WSON (5x6mm) IS25CQ032-JMLA* 16-pin SOIC 300mil (Call Factory) IS25CQ032-JBLA* 8-pin SOIC 208mil (Call Factory) IS25CQ032-JFLA* 8-pin VSOP 208mil (Call Factory) IS25CQ032-JKLA* 8-pin WSON (5x6mm) (Call Factory) IS25CQ032-JWLE KGD (Call Factory) IS25CQ032 53 ...