SST25LF020A-33-4E-SAE Microchip Technology, SST25LF020A-33-4E-SAE Datasheet - Page 10

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SST25LF020A-33-4E-SAE

Manufacturer Part Number
SST25LF020A-33-4E-SAE
Description
Flash 2 Mbit 33MHz
Manufacturer
Microchip Technology
Datasheet

Specifications of SST25LF020A-33-4E-SAE

Product Category
Flash
Rohs
yes
Memory Size
2 Mbit
Interface Type
SPI
Access Time
33 ns
Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Data Sheet
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz
is initiated by executing an 8-bit command, 0BH, followed
by address bits [A
remain active low for the duration of the High-Speed-Read
cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
©2010 Silicon Storage Technology, Inc.
SCK
CE#
FIGURE 6: High-Speed-Read Sequence
SO
SI
MODE 3
MODE 0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
MSB
0 1 2 3 4 5 6 7 8
23
-A
0
] and a dummy byte. CE# must
0B
HIGH IMPEDANCE
MSB
ADD.
15 16
ADD.
23 24
ADD.
10
IL
or V
31 32
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
2 Mbit density, once the data from address location
03FFFFH has been read, the next output will be from
address location 000000H.
IH
)
X
39 40
MSB
D
OUT
N
47 48
D
N+1
OUT
2 Mbit SPI Serial Flash
55 56
D
N+2
OUT
63 64
SST25LF020A
D
N+3
OUT
S71242-07-000
71 72
D
N+4
OUT
1242 F05.0
80
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