SST25VF040B-20-4C-QAE Microchip Technology, SST25VF040B-20-4C-QAE Datasheet - Page 11

• Manufacturer Part Number: SST25VF040B-20-4C-QAE
• Description: Flash 512K X 8 14 us
• Manufacturer: Microchip Technology

Specifications of SST25VF040B-20-4C-QAE

• Product Category: Flash
• Rohs: yes
• Memory Size: 4 Mbit
• Interface Type: SPI
• Access Time: 20 ns
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
High-Speed-Read (50/80 MHz)
Byte-Program
The High-Speed-Read instruction supporting up to 50 MHz (for SST25VF040B-50-xx-xxF) or 80 MHz
(for SST25VF040B-80-xx-xxE) Read is initiated by executing an 8-bit command, 0BH, followed by
address bits [A
Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-
fied address location. The data output stream is continuous through all addresses until terminated by a
low to high transition on CE#. The internal address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. Once the data from
address location 7FFFFH has been read, the next output will be from address location 00000H.
Figure 6: High-Speed-Read Sequence
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
Figure 7: Byte-Program Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
Note: X =
MSB
0 1 2 3 4 5 6 7 8
Dummy Byte: 8 Clocks Input Dummy Cycle (V
23
-A
SCK
0
CE#
] and a dummy byte. CE# must remain active low for the duration of the High-
SO
0B
SI
MODE 3
MODE 0
HIGH IMPEDANCE
MSB
MSB
0 1 2 3 4 5 6 7 8
ADD.
15 16
02
11
ADD.
23 24
IL
HIGH IMPEDANCE
ADD.
or V
MSB
IH
31 32
ADD.
)
X
15 16
4 Mbit SPI Serial Flash
39 40
MSB
ADD.
23
D
-A
OUT
N
23 24
0
47 48
]. Following the address, the data is
ADD.
D
N+1
OUT
31 32
55 56
MSB
1295 ByteProg.0
D
D
SST25VF040B
BP
IN
N+2
OUT
LSB
39
63 64
for the completion of
D
N+3
S71295-06-000
OUT
71 72
Data Sheet
1295 HSRdSeq.0
D
N+4
OUT
80
02/11