MC100LVELT23DG ON Semiconductor, MC100LVELT23DG Datasheet

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MC100LVELT23DG

Manufacturer Part Number
MC100LVELT23DG
Description
IC TRANSLATOR DUAL 3.3V 8SOIC
Manufacturer
ON Semiconductor
Series
100LVELTr
Datasheet

Specifications of MC100LVELT23DG

Logic Function
Translator
Number Of Bits
2
Input Type
LVPECL, LVDS
Output Type
LVTTL
Number Of Channels
2
Number Of Outputs/channel
1
Differential - Input:output
Yes/No
Propagation Delay (max)
2.5ns
Voltage - Supply
3 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Supply Voltage
3 V ~ 3.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Lead Free Status / Rohs Status
Compliant
Other names
MC100LVELT23DGOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100LVELT23DG
Manufacturer:
ON Semiconductor
Quantity:
900
MC100LVELT23
3.3 V Dual Differential
LVPECL/LVDS to LVTTL
Translator
Description
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels
are used only +3.3 V and ground are required. The small outline 8-lead
package and the dual gate design of the LVELT23 makes it ideal for
applications which require the translation of a clock and a data signal.
there are no LVPECL outputs or an external V
LVELT23 does not require both ECL standard versions. The LVPECL
inputs are differential. Therefore, the MC100LVELT23 can accept any
standard differential LVPECL input referenced from a V
Features
© Semiconductor Components Industries, LLC, 2010
August, 2010 − Rev. 18
The MC100LVELT23 is a dual differential LVPECL/LVDS to
The LVELT23 is available in only the ECL 100K standard. Since
with GND = 0 V
2.0 ns Typical Propagation Delay
Maximum Frequency > 180 MHz
Differential LVPECL Inputs
PECL Mode Operating Range:V
24 mA LVTTL Outputs
Flow Through Pinouts
Internal Pulldown and Pullup Resistors
Pb−Free Packages are Available
CC
= 3.0 V to 3.8 V
BB
reference, the
CC
of +3.3 V.
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
CASE 506AA
CASE 948R
MN SUFFIX
*For additional marking information, refer to
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
(Note: Microdot may be in either location)
Application Note AND8002/D.
SOIC−8
8
DFN8
1
ORDERING INFORMATION
1
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
http://onsemi.com
Publication Order Number:
DIAGRAMS*
MC100LVELT23/D
8
1
MARKING
8
1
ALYWG
1
KVT23
ALYW
KR23
G
G
4

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MC100LVELT23DG Summary of contents

Page 1

MC100LVELT23 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package ...

Page 2

LVPECL LVTTL Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V PECL Power Supply CC V Input Voltage I I Output Current out T Operating Temperature Range A T Storage Temperature stg Thermal Resistance (Junction−to−Ambient Thermal Resistance (Junction−to−Case) JC Thermal Resistance ...

Page 4

Table 5. LVTTL OUTPUT DC CHARACTERISTICS Symbol Characteristic V Output HIGH Voltage (I = −3.0 mA) (Note Output LOW Voltage ( mA) (Note Output Short Circuit Current OS NOTE: Device ...

Page 5

... ORDERING INFORMATION Device MC100LVELT23D MC100LVELT23DG MC100LVELT23DR2 MC100LVELT23DR2G MC100LVELT23DT MC100LVELT23DTG MC100LVELT23DTR2 MC100LVELT23DTRG MC100LVELT23MNRG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... 0.30 NOTE 3 0.05 C *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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