MAX9210EUM Maxim Integrated, MAX9210EUM Datasheet - Page 13

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MAX9210EUM

Manufacturer Part Number
MAX9210EUM
Description
Serializers & Deserializers - Serdes 21-Bit DC-Balanced Deserializer
Manufacturer
Maxim Integrated
Type
Deserializerr
Datasheet

Specifications of MAX9210EUM

Data Rate
600 Mbit/s
Input Type
LVDS
Output Type
LVCMOS/LVTTL
Number Of Inputs
3
Number Of Outputs
21
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-48 EP
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX9210EUM
Manufacturer:
MAXIM/美信
Quantity:
20 000
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock time specification. When the PLL is locking, the
outputs are low.
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
V
quency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer printed-
circuit board (PCB) with separate layers for power,
ground, LVDS inputs, and digital signals is recom-
mended.
The MAX9210/MAX9214/MAX9220/MAX9222 ESD toler-
ance is rated for IEC 61000-4-2, Human Body Model and
ISO 10605 standards. IEC 61000-4-2 and ISO 10605
specify ESD tolerance for electronic systems. The IEC
61000-4-2 discharge components are C
CC
, V
CCO
, PLL V
Input Clock and PLL Lock Time
______________________________________________________________________________________
CC
, and LVDS V
Power-Supply Bypassing
Cables and Connectors
CC
ESD Protection
Board Layout
pin with high-fre-
S
= 150pF and
PWRDWN
Programmable DC-Balance
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 15. Human Body ESD Test Circuit
Figure 16. ISO 10605 Contact Discharge ESD Test Circuit
R
inputs are rated for ±8kV Contact Discharge and ±15kV
Air Discharge. The Human Body Model discharge com-
ponents are C
the Human Body Model, all pins are rated for ±5kV
Contact Discharge. The ISO 10605 discharge compo-
nents are C
10605, the LVDS inputs are rated for ±8kV Contact
Discharge and ±25kV Air Discharge.
PWRDWN is 5V tolerant and is internally pulled down to
GND. DCB/NC is not 5V tolerant. The input voltage
range for DCB/NC is nominally ground to V
Normally, DCB/NC is connected to V
D
= 330Ω (Figure 14). For IEC 61000-4-2, the LVDS
VOLTAGE
VOLTAGE
VOLTAGE
SOURCE
SOURCE
SOURCE
HIGH-
HIGH-
HIGH-
21-Bit Deserializers
DC
DC
DC
S
= 330pF and R
S
CHARGE-CURRENT-
CHARGE-CURRENT-
CHARGE-CURRENT-
LIMIT RESISTOR
LIMIT RESISTOR
LIMIT RESISTOR
= 100pF and R
50Ω TO 100Ω
50Ω TO 100Ω
1MΩ
150pF
100pF
330pF
C
C
C
S
S
S
RESISTANCE
D
RESISTANCE
RESISTANCE
DISCHARGE
DISCHARGE
DISCHARGE
STORAGE
CAPACITOR
STORAGE
CAPACITOR
STORAGE
CAPACITOR
330Ω
1.5kΩ
2kΩ
= 2kΩ (Figure 16). For ISO
R
R
D
R
D
D
D
= 1.5kΩ (Figure 15). For
5V Tolerant Input
CC
or ground.
DEVICE
UNDER
DEVICE
UNDER
DEVICE
UNDER
TEST
TEST
TEST
CC
13
.

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