MAX9210ETM-T Maxim Integrated, MAX9210ETM-T Datasheet - Page 11

• Manufacturer Part Number: MAX9210ETM-T
• Description: Serializers & Deserializers - Serdes 21-Bit DC-Balanced Deserializer
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9210ETM-T

• Data Rate: 600 Mbit/s
• Input Type: LVDS
• Output Type: LVCMOS/LVTTL
• Number Of Inputs: 3
• Number Of Outputs: 21
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFN-48
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

series capacitors is (C x (R
RC time constant for four equal-value series capacitors
is (C x (R
R
ance (usually 100Ω) and R
driver design (the minimum differential output resis-
tance of 78Ω for the MAX9209/MAX9213 serializers is
used in the following example). This leaves the capaci-
tor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
where:
C = AC-coupling capacitor (F).
t
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
R
R
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
B
T
T
O
= bit time (s).
= termination resistor (Ω).
C = - (2 x t
is required to match the transmission line imped-
= output resistance (Ω).
T
+ R
PWRDWN
TxCLK IN
B
TxIN
O
))/4 (Figure 13).
x DSV)/(ln (1 - D) x (R
______________________________________________________________________________________
7
7
7
(7 + 2):1
(7 + 2):1
(7 + 2):1
O
PLL
T
is determined by the LVDS
+ R
21:3 SERIALIZER
MAX9209
MAX9213
O
))/2 (Figure 12). The
T
+ R
O
)) (Eq 1)
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
TxCLK OUT
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
HIGH-FREQUENCY, CERAMIC
Programmable DC-Balance
Equation 1 is for two series capacitors (Figure 12). The
bit time (t
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 13).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
Jitter due to droop is proportional to the droop and
transition time:
where:
t
t
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
J
T
C = - (2 x t
C = - (2 x 13.9ns x 10)/(ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.0773µF
= jitter (s).
= transition time (s) (0 to 100%).
100Ω
100Ω
100Ω
100Ω
RxCLK IN
RxIN
21-Bit Deserializers
B
) is the period of the parallel clock divided by
B
x DSV)/(ln (1 - D) x (R
3:21 DESERIALIZER
MAX9210
MAX9214
MAX9220
MAX9222
t
J
t
J
= t
= 1ns x 0.02
t
J
T
= 20ps
x D (Eq 2)
1:(9 - 2)
1:(9 - 2)
1:(9 - 2)
PLL
T
7
7
7
+ R
RxOUT
PWRDWN
RxCLK OUT
O
))
11