MAX3107ETG/V+ Maxim Integrated, MAX3107ETG/V+ Datasheet - Page 13

• Manufacturer Part Number: MAX3107ETG/V+
• Description: UART Interface IC UART
• Manufacturer: Maxim Integrated

Specifications of MAX3107ETG/V+

• Number Of Channels: 1
• Data Rate: 24 Mbps
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V
• Supply Current: 4 mA

Maxim Integrated
TQFN-EP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
7
8
9
PIN
SSOP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
1
2
3
RTS/CLKOUT
DIN/A1
NAME
DGND
GPIO0
GPIO1
GPIO2
GPIO3
AGND
XOUT
V
CTS
IRQ
RST
XIN
RX
V
EP
V
TX
EXT
SPI/I
A
L
Serial-Data and Address 1 Input. When I2C/SPI is high, DIN/A1 functions as the DIN
SPI serial-data input. When I2C/SPI is low, DIN/A1 functions as the A1 I
address programming input and connects to DIN/A1 DGND or V
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is
pending.
Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode.
In hardware reset mode, the oscillator and the internal PLL are shut down; there is no
clock activity.
Digital Interface Logic-Level Supply. V
RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, and I2C/SPI. Bypass V
with a 0.1FF ceramic capacitor to DGND. V
Digital Ground
General-Purpose Input/Output 0. GPIO0 is user programmable as an input or output
(push-pull or open drain). GPIO0 has a weak pulldown resistor to ground.
General-Purpose Input/Output 1. GPIO1 is user programmable as an input or output
(push-pull or open drain). GPIO1 has a weak pulldown resistor to ground.
General-Purpose Input/Output 2. GPIO2 is user programmable as an input or output
(push-pull or open drain). GPIO2 has a weak pulldown resistor to ground.
General-Purpose Input/Output 3. GPIO3 is user programmable as an input or output
(push-pull or open drain). GPIO3 has a weak pulldown resistor to ground.
Active-Low Clear-to-Send Input. CTS is a flow-control input.
Active-Low Request-to-Send Output. RTS/CLKOUT can be set high or low by pro-
gramming bit 7 (RTS) of the LCR register.
Receive Input. Serial UART data input. RX has an internal weak pullup resistor to V
Transmit Output. Serial UART data output.
Transceiver Interface Level Supply. V
RX, TX, RTS, CTS, and GPIO_. Bypass V
DGND.
Crystal Output. When using an external crystal, connect one end of the crystal to
XOUT and the other to XIN. When using an external clock source, leave XOUT
unconnected.
Crystal/Clock Input. When using an external crystal, connect one end of the crystal to
XIN and the other one to XOUT. When using an external clock source, drive XIN with
the external clock.
Analog Ground
Analog Supply. V
ic capacitor to AGND.
Exposed Paddle. Connect EP to AGND. EP is not intended as an electrical connec-
tion point. Only for TQFN-EP package.
2
C UART with 128-Word FIFOs
A
powers the PLL and internal LDO. Bypass V
Pin Descriptions (continued)
FUNCTION
EXT
L
powers the internal logic-level translators for
EXT
powers the internal logic-level translators for
L
with a 0.1FF ceramic capacitor to
must be powered in all modes.
MAX3107
A
L
with a 0.1FF ceram-
.
2
C device
EXT
.
L
13