STM8AF628ATCY STMicroelectronics, STM8AF628ATCY Datasheet - Page 108

• Manufacturer Part Number: STM8AF628ATCY
• Description: 8-bit Microcontrollers - MCU 8-Bit Automotive MCU EEPROM 128kb Flash
• Manufacturer: STMicroelectronics

Specifications of STM8AF628ATCY

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: STM8A
• Data Bus Width: 8 bit

Revision history
108/110
Table 57.
3&-Jan-2011
18-Jul-2012
Date
Document revision history (continued)
(continued)
Revision
Rev 8
Rev 9
Renamed Fast Active Halt mode to Active-halt mode with regulator
on, and Slow Active Halt mode to Active-halt mode with regulator off,
updated
Total current consumption in Halt and Active-halt modes. General
conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise
stated. I
renamed t
Removed note 1 in
1 below
Removed note 3 in
and Slow mode. General conditions for VDD apply, TA = -40 °C to
150
Removed note 2 in
Table 37: Flash program memory/data EEPROM
Removed note 1 in
value in
memory.
Added t
characteristics.
Added recommendation concerning NRST pin level, and power
consumption sensitive applications, above
Recommended reset pin
value.
Update
specifications.
Updated
Moved know limitations to separate errata sheet.
Added “not recommended for new design” note to device family 51,
memory size 7 and 9, and temperature range B, in
Ordering information
Added Raisonance compiler in
Updated wildcards of document part numbers.
Added VFQFPN package.
Added STM8AF62A6 part number.
Table 1: Device
Table 2: STM8AF52xx product line-up with CAN
STM8AF62xx product line-up without
order codes; updated size of data EEPROM for 64K devices to 2K
instead of 1.5K; updated RAM.
Figure 1: STM8A block
removed PDR; added legend.
Section 5.4: Flash program and data
nonrelevant bullet points and added a sentence about the factory
programme.
Added
updated
ADC
Table 14: Memory model
addresses, and stack roll-over addresses; updated footnote 1.
Doc ID 14395 Rev 9
°C.
features: updated ADC input range.
Table 6: Peripheral clock gating bits (CLK_PCKENR1)
IFP(NRST)
DD(FAH)
Note 1
Figure 10: fCPUmax versus
Table 38: Flash program memory
Section 5.6: Low-power operating
Table 7: Peripheral clock gating bits
Note 1
WU(AH)
in
and I
summary: updated footnote
in
.
and renamed V
Table 42: TIM 1, 2, 3, and 4 electrical
Table 43: SPI
Table 26: General operating
Table 28: Total current consumption in Run, Wait
Table 33: HSE external clock characteristics
Table 39: Data
DD(SAH)
scheme(1).
diagram: updated POR, BOR and WDG;
protection, and updated external capacitor
128K: updated RAM size, RAM end
renamed I
Changes
STM8AF52/62xx, STM8AF51/61xx
Section 13.2: Software
F(NRST)
characteristics.
memory. Modified T
VDD.
EEPROM: removed
CAN: added “P” version for all
DD(AH);
t
IFP
and
Figure 38:
modes, and
1
in
(CLK_PCKENR2).
and added footnote 2.
t
Table 39: Data
Table 41: NRST pin
WU(FAH)
conditions, and note
and
memory.
Figure 52:
Table 3:
WE
tools.
and t
Table 29:
maximum
WU(SAH)
and
and