MAX7301AAX-T Maxim Integrated, MAX7301AAX-T Datasheet - Page 6

• Manufacturer Part Number: MAX7301AAX-T
• Description: Interface - I/O Expanders 2.5-5.5V 20/28 Port I/O Expander
• Manufacturer: Maxim Integrated
• Series: MAX7301r

Specifications of MAX7301AAX-T

• Maximum Operating Frequency: 26 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-36
• Output Current: 4.5 mA, 18 mA
• Power Dissipation: 941 mW

The MAX7301 communicates through an SPI-compati-
ble 4-wire serial interface. The interface has three
inputs, Clock (SCLK), Chip Select
(DIN), and one output, Data Out (DOUT). CS must be
low to clock data into or out of the device, and DIN
must be stable when sampled on the rising edge of
SCLK. DOUT provides a copy of the bit that was input
15.5 clocks earlier, or upon a query it outputs internal
register data, and is stable on the rising edge of SCLK.
Note that the SPI protocol expects DOUT to be high
impedance when the MAX7301 is not being
accessed; DOUT on the MAX7301 is never high
impedance. See www.maxim-ic.com/an 1879 for
ways to convert DOUT to tri-state, if required.
SCLK and DIN may be used to transmit data to other
peripherals, so the MAX7301 ignores all activity on
SCLK and DIN except between the fall and subsequent
rise of CS.
Controlling the MAX7301 requires sending a 16-bit
word. The first byte, D15 through D8, is the command
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
28-Port I/O Expander
Table 2. Port Configuration Matrix
Table 1. Port Configuration Map
6
Output
Port Configuration for P7, P6, P5, P4
Port Configuration for P11, P10, P9, P8
Port Configuration for P15, P14, P13, P12
Port Configuration for P19, P18, P17, P16
Port Configuration for P23, P22, P21, P20
Port Configuration for P27, P26, P25, P24
Port Configuration for P31, P30, P29, P28
MODE
Input
Input
_______________________________________________________________________________________
Control and Operation Using the
GPIO Input with Pullup
Without Pullup
GPIO Output
FUNCTION
GPIO Input
REGISTER
DO NOT USE THIS SETTING
4-Wire Interface
Serial Interface
input logic level
Register bit = 0
Register bit = 1
(0xA0–0xDF)
Register bit =
(0x20–0x5F)
REGISTER
(CS), and Data In
PORT
CODE (HEX)
ADDRESS
Active-low logic output
Active-high logic output
Schmitt logic input
Schmitt logic input with pullup
0x0A
0x0B
0x0C
0x0D
0x09
0x0E
0x0F
PIN BEHAVIOR
address (Table 3), and the second byte, D7 through
D0, is the data byte (Table 4 through Table 8).
Multiple MAX7301s may be daisy-chained by connect-
ing the DOUT of one device to the DIN of the next, and
driving SCLK and CS lines in parallel (Figure 3). Data at
DIN propagates through the internal shift registers and
appears at DOUT 15.5 clock cycles later, clocked out
on the falling edge of SCLK. When sending commands
to multiple MAX7301s, all devices are accessed at the
same time. An access requires (16
where n is the number of MAX7301s connected togeth-
er. To update just one device in a daisy-chain, the user
can send the No-Op command (0x00) to the others.
The MAX7301 contains a 16-bit shift register into which
DIN data are clocked on the rising edge of SCLK, when
CS is low. When CS is high, transitions on SCLK have
no effect. When CS goes high, the 16 bits in the Shift
register are parallel loaded into a 16-bit latch. The 16
bits in the latch are then decoded and executed.
D7
P11
P15
P19
P23
P27
P31
P7
D6
Connecting Multiple MAX7301s
D5
P10
P14
P18
P22
P26
P30
P6
REGISTER DATA
CODE (HEX)
0x09 to 0x0F
0x09 to 0x0F
0x09 to 0x0F
0x09 to 0x0F
ADDRESS
Writing Device Registers
D4
D3
to the 4-Wire Bus
P13
P17
P21
P25
P29
P5
P9
UPPER
CONFIGURATION
✕
D2
0
0
1
1
n) clock cycles,
BIT PAIR
PORT
D1
LOWER
P12
P16
P20
P24
P28
P4
P8
0
1
0
1
D0