MAX9969BDCCQ+TD Maxim Integrated, MAX9969BDCCQ+TD Datasheet - Page 25

• Manufacturer Part Number: MAX9969BDCCQ+TD
• Description: Interface - Specialized
• Manufacturer: Maxim Integrated
• Series: MAX9969r

Specifications of MAX9969BDCCQ+TD

• Product Type: ATE Driver/Comparator
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100 EP
• Minimum Operating Temperature: 0 C

Table 1. Driver Logic
Table 2. Slew-Rate Logic
LLEAK control the switching. In high-impedance mode,
the bias current at DUT_ is less than 3µA over the 0 to
3V range, while the node maintains its ability to track
high-speed signals. In low-leakage mode, the bias cur-
rent at DUT_ is further reduced to less than 15nA, and
signal tracking slows. See the Low-Leakage Mode,
LLEAK section for more details.
The nominal driver output resistance is 50Ω. Contact
the factory for different resistance values within the
45Ω to 51Ω range.
Configure the voltage clamps (high and low) to limit the
voltage at DUT_ and to suppress reflections when the
channel is configured as a high-impedance receiver.
The clamps behave as diodes connected to the out-
puts of high-current buffers. Internal circuitry compen-
sates for the diode drop at 1mA clamp current. Set the
clamp voltages using the external connections CPHV_
and CPLV_. The clamps are enabled only when the dri-
ver is in high-impedance mode (Figure 2). For transient
suppression, set the clamp voltages to approximately
the minimum and maximum expected DUT_ voltage
range. The optimal clamp voltages are application spe-
cific and must be empirically determined. If clamping is
CONNECTIONS
DATA
EXTERNAL
X
X
X
1
0
SC1
0
0
1
1
RCV
X
0
0
1
1
SC0
0
1
0
1
TMSEL LLEAK
______________________________________________________________________________________
REGISTER
INTERNAL
CONTROL
X
X
1
0
X
DRIVER SLEW RATE (%)
0
0
0
0
1
Driver/Comparator with 35mA Load
High-impedance mode
Low-leakage mode
Dual, Low-Power, 1200Mbps ATE
100
Drive to DHV_
Drive to DLV_
Drive to DTV_
75
50
25
(term mode)
OUTPUT
DRIVER
(high-Z)
Clamps
not desired, set the clamp voltages at least 0.7V out-
side the expected DUT_ voltage range; overvoltage
protection remains active without loading DUT_.
The MAX9969 provides two independent high-speed
comparators for each channel. Each comparator has
one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (see the
Functional Diagram). Comparator outputs are a logical
result of the input conditions, as indicated in Tables 3a
and 3b.
The comparator differential outputs are open-collector
outputs to ease interfacing with a wide variety of logic
families. Versions with and without internal termination
resistors switch an 8mA current source between the
two outputs (Figure 3). The optional termination resis-
tors connect the outputs to voltage input V
versions without internal termination, leave V
unconnected and add the required external resistors.
These resistors are typically 50Ω to the pullup voltage
at the receiving end of the output trace. Alternate con-
figurations can be used provided that the Absolute
Maximum Ratings are not exceeded. For versions with
internal termination, connect V
voltage. Each output provides a nominal 400mV
swing and 50Ω source termination.
The upper comparators are configurable as differential
receivers for LVDS and other differential DUT_ signals.
When mode bit CDIFF is asserted, the upper compara-
tor inputs are routed from the DUT_ outputs for both
channels.
Table 3a. Comparator Logic, CDIFF = 0
Table 3b. Comparator Logic, CDIFF = 1
DUT_ > CHV_ DUT_ > CLV_
DUT1 > DUT2 DUT_ > CLV_
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CL_, NCL_
CL_, NCL_
CCO
0
1
0
1
0
1
0
1
_ to the desired V
Comparators
CH_, NCH_
CH_, NCH_
CCO
0
0
1
1
0
0
1
1
_. For
CCO
P-P
OH
25
_