MAX98355AEWL+ Maxim Integrated, MAX98355AEWL+ Datasheet - Page 18

• Manufacturer Part Number: MAX98355AEWL+
• Description: Audio Amplifiers PCM Input Class D Audio Power Amp
• Manufacturer: Maxim Integrated

Specifications of MAX98355AEWL+

• Rohs: yes
• Product: Class-D
• Output Power: 3.2 W
• Thd Plus Noise: 0.013 %
• Operating Supply Voltage: 2.5 V to 5.5 V
• Supply Current: 2.5 mA
• Maximum Power Dissipation: 1096 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: WLP-9
• Minimum Operating Temperature: - 40 C

The MAX98355A follows standard I
a delay of one BCLK cycle after the LRCLK transition
before the beginning of a new data word
Figure
specification by aligning the LRCLK transitions with the
beginning of a new data word
Figure 8
frame-sync pulse is used for LRCLK. In TDM mode, there
must be 32, 48, or 64 BCLK cycles per LRCLK. In TDM
Figure 4. MAX98355A I
I
I
I
LRLCK
LRLCK
LRLCK
2
2
2
S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = LOGIC-HIGH
S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = PULLUP THROUGH R
S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = PULLUP THROUGH R
BCLK
BCLK
BCLK
DIN
DIN
DIN
5). The MAX98355B follows the left justified timing
and
Figure 9
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D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
PCM Input Class D Audio Power Amplifiers
2
S Digital Audio Interface Timing, 16-Bit Resolution
show TDM operation, in which a
PCM Timing Characteristics
(Figure 6
LEFT
LEFT
LEFT
IGNORED
2
S timing by allowing
and
(Figure 4
Figure
SMALL
LARGE
7).
and
LEFT AND RIGHT AVERAGED
MAX98355A/MAX98355B
mode, the IC only accepts 16-bit formatted data and only
the first two TDM slots can be selected. However, if the
first 16 bits are selected (SD_MODE = logic-high), then the
bit-depth or number of channels has no effect as long as
there are 32, 48, or 64 BCLK cycles per LRCLK. All extra
bits in the frame are ignored
If the second 16 bits are selected (SD_MODE = logic-
high through R
data and cannot include more than 4 channels (64 BCLK
cycles). TDM operation is available in both ICs.
SMALL
RIGHT
RIGHT
RIGHT
IGNORED
), then the TDM data must be 16-bit
(Figure 10
and
LEFT
LEFT
LEFT
IGNORED
Figure
11).