AN30183A-PR Panasonic Electronic Components, AN30183A-PR Datasheet - Page 25

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AN30183A-PR

Manufacturer Part Number
AN30183A-PR
Description
Low Dropout Controllers - LDO Vout 0.8-2.4 600mA 1Ch DCDC 4Ch LDO I2C
Manufacturer
Panasonic Electronic Components
Datasheet

Specifications of AN30183A-PR

Rohs
yes
Input Voltage Max
5.5 V
Output Voltage
0.8 V to 2.4 V
Output Current
600 mA
Load Regulation
20 mV
Number Of Outputs
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
XBGA-20
Input Voltage Min
2.5 V
Maximum Power Dissipation
0.348 W
Minimum Operating Temperature
- 30 C
OPERATION
1. I
This IC, I2C-bus, is designed to correspond to the
Standard-mode (100 kbps) and Fast-mode(400 kbps)
devices in the version 2.1 of NXP's specification.
However, it does not correspond to the HS-mode (to 3.4
Mbps). This IC will operate as a slave device in the I
bus system. This IC will not operate as a master device.
The program operation check of this IC has not been
conducted on the multi-master bus system and the mix-
speed bus system, yet. The connected confirmation of
this IC to the CBUS receiver also has not been checked.
Please confirm with our company if the IC will be used in
these mode systems. The I
A High to Low transition on the SDA line while SCL is
High is one such unique case. This situation indicates
START condition. A Low to High transition on the SDA
line while SCL is High defines STOP condition.
START and STOP conditions are always generated by
the master. After START condition occur, the bus will be
busy. The bus is considered to be free again a certain
time after the STOP condition.
Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most
significant bit (MSB) first.
SDA
SCL
SDA
SCL
START condition
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
repeated START
2
Sr
START or
or
C-bus Interface
S
condition
a.) Basic Rules
b.) START and STOP conditions
MSB
1
2
acknowledgement
signal from slave
7
8
ACK
9
2
C is the brand of NXP.
1
signal from receiver
acknowledgement
2 3 – 8 9
repeated START
STOP condition
ACK
STOP or
condition
Sr
Sr
or
P
2
P
C-
25
Condition
Condition
Condition
Write
Read
Slave Address
Write mode
Read mode
Start
Start
Start
Sub-address should be assigned first.
d.) Data format
Pin ASEL
When data is read without assigning sub-address, it is
possible to read the value of sub-address specified in
Write mode immediately before.
S
S
d1.) When Sub address is not specified
d2.) When Sub address is specified
S
High
Low
Ex) When writing data into address and reading data
from "01 h".
Slave Address
Address
Slave
Write Mode : 0
S
S
Slave Address
Address
Address
A6
Slave
Slave
1
1
Write mode : 0
0
Acknowledge Bit
A
A5
1
1
Address
W
Read mode : 1
Sub
Ack
A4
A
1
0
1
1
A
A
Sub Address
Ack
A3
R
Sub Address
0
0
Repeated
Start
Condition
Data Byte
A
Ack
AN30183A
A
S
A2
01h
0
0
Address
Slave
A1
1
1
Data byte
A
A
A P
Read Mode : 1
A0
0
1
1
Data Byte
Data Byte
Ack
A
R/W
Data Byte
x
x
Condition
Condition
Ver. AEB
6Eh
Hex
6Fh
Stop
condition
A
Stop
A
Stop
A
A
P
P
P
P

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