72211L15J IDT, 72211L15J Datasheet
72211L15J
Specifications of 72211L15J
Related parts for 72211L15J
72211L15J Summary of contents
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... LOGIC WRITE POINTER RESET LOGIC RS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
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... IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 PIN CONFIGURATION INDEX PAF 3 4 PAE GND 5 REN1 6 RCLK 7 REN2 TQFP (PR32-1, order code: PF) ...
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... IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating Com'l & Ind'l V Terminal Voltage with –0.5 to +7.0 TERM Respect to GND T Storage Temperature –55 to +125 STG I DC Output Current ...
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... Almost-Empty Flag & Programmable Almost-Full Flag NOTES: 1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. AC TEST CONDITIONS In Pulse Levels ...
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... Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full. The FIFO is configured to have programmable flags when the Write Enable 2/Load (WEN2/LD) is set LOW at Reset (RS=LOW). The IDT72421/72201/ 72211/72221/72231/72241/72251 devices contain four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values ...
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... Full Offset (LSB) Default Value 007H 8 3 (MSB) 0000 Figure 3. Offset Register Location and Default Values 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72201 - 256 x 9-BIT 7 0 Empty Offset (LSB) Reg. Default Value 007H Full Offset (LSB) Reg. Default Value 007H 0 IDT72221 - 1,024 x 9-BIT ...
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... The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72421, 256 writes for the IDT72201, 512 writes for the IDT72211, 1,024 writes for the IDT72221, 2,048 writes for the IDT72231, 4,096 writes for the IDT72241, and 8,192 writes for the IDT72251 ...
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... IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 REN1, REN2 WEN1 (1) WEN2/LD EF, PAE FF, PAF NOTES: 1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers ...
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... IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 RCLK t ENS t ENH REN1, REN2 OLZ OE WCLK WEN1 WEN2 NOTE: is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK 1 ...
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... IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 WRITE WCLK t SKEW1 WEN1 WEN2 (If Applicable) RCLK t ENH t ENS REN1, REN2 OE LOW DATA IN OUTPUT REGISTER 0 8 NOTE: 1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO. ...
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... NOTES PAF offset . 2. 64-m words in FIFO for IDT72421, 256-m words for IDT72201, 512-m words for IDT72211, 1,024-m words for IDT72221, 2,048-m words for IDT72231, 4,096-m words for IDT72241, and 8,192-m words for IDT72251. is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and 3 ...
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... IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN1 PAE OFFSET (LSB) t CLK t t CLKH CLKL RCLK t ENS LD t ENS ...
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... WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the endpoint status flags (EF and FF). The partial status flags (AE and AF) can be detected from any one device ...
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... SyncFIFO 72221 2,048 x 9 ⎯ SyncFIFO 72231 4,096 x 9 ⎯ SyncFIFO 72241 8,192 x 9 ⎯ SyncFIFO 72251 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 14 Clock Cycle Time (t ) CLK Speed in Nanoseconds 2655 drw18 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ...