7202LA12SO IDT, 7202LA12SO Datasheet

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7202LA12SO

Manufacturer Part Number
7202LA12SO
Description
FIFO
Manufacturer
IDT
Datasheet

Specifications of 7202LA12SO

Part # Aliases
IDT7202LA12SO

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Part Number
Manufacturer
Quantity
Price
Part Number:
7202LA12SOG
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
7202LA12SOG
Quantity:
10
©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES:
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FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1,024 x 9 organization (IDT7202)
Low power consumption
— Active: 440mW (max.)
—Power-down: 28mW (max.)
Ultra high speed—12ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
720x family is pin and functionally compatible from 256 x 9 to 64k x 9
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS™ technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666, 5962-89863
Dual versions available in the TSSOP package. For more informa-
and 5962-89536 are listed on this function
tion, see IDT7280/7281/7282 data sheet
IDT7280 = 2 x IDT7200
IDT7281 = 2 x IDT7201
IDT7282 = 2 x IDT7202
W
XI
R
CONTROL
CONTROL
WRITE
READ
CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
EXPANSION
LOGIC
LOGIC
FLAG
POINTER
WRITE
THREE-
STATE
BUFFERS
1
DATA OUTPUTS
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• • • • •
DESCRIPTION:
on a first-in/first-out basis. The devices use Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for unlimited expansion
capability in both word size and depth.
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
are designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications. Military grade
product is manufactured in compliance with MIL-STD-883, Class B.
DATA INPUTS
The IDT7200/7201/7202 are dual-port memories that load and empty data
The reads and writes are internally sequential through the use of ring
The devices utilize a 9-bit wide data array to allow for control and parity bits
These FIFOs are fabricated using high-speed CMOS technology. They
Industrial temperature range (–40
(plastic packages only)
Green parts available, see ordering information
(D
1,024 x 9
(Q
ARRAY
256 x 9
512 x 9
0
RAM
-D
0
-Q
8
)
8
)
EF
XO/HF
FF
POINTER
READ
RESET
LOGIC
FL/RT
RS
2679 drw 01
o
C to +85
o
C) is available
IDT7201LA
IDT7202LA
JUNE 2012
IDT7200L
DSC-2679/13

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7202LA12SO Summary of contents

Page 1

... CONTROL R CONTROL XI IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES ©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 Industrial temperature range (– ...

Page 2

... P28-2 CERDIP D28-1 (1) THIN CERDIP D28-3 SOIC SO28-3 TOP VIEW NOTE: 1. The 600-mil-wide DIP (P28-1 and D28-1) and LCC are not available for the IDT7200. ABSOLUTE MAXIMUM RATINGS Symbol Rating Com’l & Ind'l V Terminal Voltage –0.5 to +7.0 TERM with Respect to GND ...

Page 3

... CC1 (5,8) I Standby Current (R=W=RS=FL/RT=V CC2 NOTES: 1. Industrial temperature range product for the 15ns and 25 ns speed grades are available as a standard device. 2. Military speed grades of 50ns and 80ns are only available for the IDT7201LA. 3. Measurements with 0.4 ≤ V ≤ ≥ 0.4 ≤ V ≤ ...

Page 4

... Timings referenced Test Conditions. 2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode ( ± ...

Page 5

... XI Set-up Time XIS NOTES: 1. Timings referenced Test Conditions 2. Military speed grades of 50ns and 80ns are only available for IDT7201LA. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode. ...

Page 6

... If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go LOW after 256 writes for IDT7200, 512 writes for the IDT7201A and 1,024 writes for the IDT7202A. ...

Page 7

... IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 HF, FF NOTES: 1. EF, FF, HF may change status during Reset, but flags will be valid and around the rising edge of RS RLZ ...

Page 8

... IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 LAST READ IGNORED READ REF DATA OUT VALID RT W,R HF, EF Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse ...

Page 9

... XIS READ FROM FIRST PHYSICAL LOCATION Figure 11. Expansion In depth can be attained by adding additional IDT7200/7201A/7202As. These FIFOs operate in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. ...

Page 10

... WRITE (W) FULL FLAG (FF) RESET (RS) Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (t edge of W, called the first write edge, and it remains on the bus until the R line ...

Page 11

... IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 TABLE 1 — RESET AND RETRANSMIT Single Device Configuration/Width Expansion Mode Mode RS Reset 0 Retransmit 1 Read/Write 1 NOTE: 1. Pointer will increment if flag is HIGH. TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode ...

Page 12

... IDT7200/ IDT7201A/ IDT7202A DEPTH EXPANSION BLOCK NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13. SYSTEM ...

Page 13

... IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 DATA DATA OUT DATA IN DATA OUT t WEF t WLZ t A Figure 17. Read Data Flow-Through Mode t RFF t A DATA VALID OUT Figure 18. Write Data Flow-Through Mode 13 COMMERCIAL, INDUSTRIAL AND MILITARY ...

Page 14

... NOTES: 1. Industrial temperature range product is available for the 15ns and 25ns as a standard product. 2. "A" included for IDT7201 and IDT7202 ordering part number. 3. Green parts are available. For specific speeds and packages contact your local sales office. 4. For "P", Plastic Dip, when ordering green package, the suffix is "PDG". ...

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