72V851L10PFG IDT, 72V851L10PFG Datasheet - Page 8

• Manufacturer Part Number: 72V851L10PFG
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V851L10PFG

• Product Category: FIFO
• Rohs: yes
• Part # Aliases: IDT72V851L10PFG

TABLE 1: STATUS FLAGS FOR A AND B FIFOS
OUTPUTS
OUTPUTS: : : : :
OUTPUTS
operations, when Array A (B) is full. If no reads are performed after reset,
FFA (FFB) will go LOW after 256 writes to the IDT72V801's FIFO A (B), 512
writes to the IDT72V811's FIFO A (B), 1,024 writes to the IDT72V821's FIFO
A (B), 2,048 writes to the IDT72V831's FIFO A (B), 4,096 writes to the
IDT72V841's FIFO A (B), or 8,192 writes to the IDT72V851's FIFO A (B).
the Write Clock WCLKA (WCLKB).
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
the Read Clock RCLKA (RCLKB).
LOW when the amount of data in Array A (B) reaches the Almost-Full condition.
If no reads are performed after reset, PAFA (PAFB) will go LOW after (256-m)
writes to the IDT72V801's FIFO A (B), (512-m) writes to the IDT72V811's FIFO
A (B), (1,024-m) writes to the IDT72V821's FIFO A (B), (2,048-m) writes to
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
OUTPUTS
OUTPUTS
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of
Empty Flag (EFA, EFB) — EFA (EFB) will go LOW, inhibiting further read
EFA (EFB) is synchronized with respect to the LOW-to-HIGH transition of
Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will go
(n+1) to (256-(m+1))
(n+1) to (2,048-(m+1))
(2,048-m)
(256-m)
IDT72V801
IDT72V831
1 to n
1 to n
256
2,048
0
(2)
0
(2)
(1)
to 255
(1)
to 2,047
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
(n+1) to (4,096-(m+1))
(4,096-m)
(n+1) to (512-(m+1))
(512-m)
IDT72V811
IDT72V841
1 to n
1 to n
4,096
512
0
0
(2)
(2)
(1)
(1)
to 511
to 4,095
(n+1) to (1,024-(m+1))
(n+1) to (8,192-(m+1))
(1,024-m)
(8,192-m)
8
IDT72V821
IDT72V851
1 to n
1 to n
the IDT72V831's FIFO A (B), (4,096-m) writes to the IDT72V841's FIFO A
(B), or (8,1912-m) writes to the IDT72V851's FIFO A (B).
the Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
Registers.
of the Write Clock WCLKA (WCLKB).
go LOW when the read pointer is "n+1" locations less than the write pointer.
The offset "n" is defined in the Empty Offset Registers. If no reads are performed
after reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B).
words.
of the Read Clock RCLKA (RCLKB).
outputs for memory array A, QB
array B
1,024
8,192
0
0
(2)
(2)
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of
If there is no Full offset specified, PAFA (PAFB) will go LOW at Full-7 words.
PAFA (PAFB) is synchronized with respect to the LOW-to-HIGH transition
Programmable Almost–Empty Flag (PAEA, PAEB) — PAEA (PAEB) will
If there is no Empty offset specified, PAEA (PAEB) will go LOW at Empty+7
PAEA (PAEB) is synchronized with respect to the LOW-to-HIGH transition
Data Outputs (QA
(1)
(1)
to 1,023
to 8,191
.
TM
0
– QA
FFA
FFB
FFA
FFB
H
H
H
H
H
H
H
H
L
L
8,
QB
0
- QB
0
– QB
8
PAFA
PAFB
PAFA
PAFB
are the nine data outputs for memory
COMMERCIAL AND INDUSTRIAL
H
H
H
H
H
H
L
L
L
L
8
) — QA
TEMPERATURE RANGES
0
OCTOBER 22, 2008
PAEA
PAEB
PAEA
PAEB
- QA
H
H
H
H
H
H
L
L
L
L
8
are the nine data
EFA
EFB
EFA
EFB
H
H
H
H
H
H
H
H
L
L