MAX6960EVCMODU Maxim Integrated, MAX6960EVCMODU Datasheet - Page 20

• Manufacturer Part Number: MAX6960EVCMODU
• Description: LED Display Drivers Evaluation Kit/Evaluation System for the MAX6960
• Manufacturer: Maxim Integrated

Specifications of MAX6960EVCMODU

• Number Of Segments: 64
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Supply Current: 9 mA
• High Level Output Current: 48 mA
• Low Level Output Current: 750 mA
• Power Dissipation: 1012 mW

4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
MAX6960–MAX6963
Table 21. Global Panel Configuration—Color Control (C Data Bit D6) Format
Table 22. Global Panel Configuration—Planes/Intensity Control (PI Data Bit D7) Format
Table 23. Frame Modulation with Pixel Intensity
Table 24. Pixel Intensity Scale Register Format
20
Display panel is built with monocolor or RGB
digits (permanently set this way for MAX6962 and
MAX6963)
Display panel is built with RGY digits
Four display memory planes (0, 1, 2, 3) available;
pixel level-intensity control is 1 bit per pixel per
color (on/off) (permanently set this way for
MAX6961 and MAX6963)
Two display memory planes (0, 1) available;
pixel level-intensity control is 2 bits per pixel per
color (4 levels)
Both
Arithmetic
Geometric
Arithmetic
Geometric
Both
Both
Arithmetic
Geometric
Arithmetic
Geometric
Both
GRADUATION
GRADUATION
PIXEL
PIXEL
REGISTER
REGISTER
1
1
1
0
0
0
1
1
1
0
0
0
PIXEL
PIXEL
DATA
DATA
1
0
0
1
1
0
1
0
0
1
1
0
INTENSITY
INTENSITY
SETTING
SETTING
PIXEL
PIXEL
Full
Full
2/3
1/2
1/3
1/4
2/3
1/2
1/3
1/4
Off
Off
CODE (HEX)
CODE (HEX)
0
1
1
1
0
0
0
0
1
1
1
0
0
0
ADDRESS
ADDRESS
0x0D
0x0D
0x0D
0x0D
1
1
0
0
1
1
0
1
1
0
0
1
1
0
2
1
1
1
0
0
0
2
1
1
1
0
0
0
D7
D7
PI
PI
0
1
PATTERN OF MULTIPLEX CYCLES
PATTERN OF MULTIPLEX CYCLES
FOR WHICH A PIXEL IS ENABLED
FOR WHICH A PIXEL IS ENABLED
3
1
1
0
0
0
0
3
1
1
0
0
0
0
D6
D6
C
C
0
1
4
1
0
1
1
0
0
4
1
0
1
1
0
0
D5
D5
5
1
1
0
0
1
0
5
1
1
0
0
1
0
F
F
F
F
REGISTER DATA
REGISTER DATA
6
1
1
1
0
0
0
6
1
1
1
0
0
0
D4
D4
R
R
R
R
7
1
0
0
1
0
0
7
1
0
0
1
0
0
DP1
DP1
DP1
DP1
D3
D3
8
1
1
1
0
0
0
8
1
1
1
0
0
0
DP0
DP0
DP0
DP0
D2
D2
9
1
1
0
0
1
0
9
1
1
0
0
1
0
Maxim Integrated
D1
D1
IP
IP
IP
IP
10
10
1
0
1
1
0
0
1
0
1
1
0
0
D0
D0
S
S
S
S
11
11
1
1
0
0
0
0
1
1
0
0
0
0