MAX1366ECM Maxim Integrated, MAX1366ECM Datasheet - Page 13

• Manufacturer Part Number: MAX1366ECM
• Description: LED Display Drivers
• Manufacturer: Maxim Integrated

The MAX1366/MAX1368 analog input/reference buffers
allow the use of high-impedance signal sources. The
input buffers’ common-mode input range allows the ana-
log inputs and the reference to range from -2.2V to +2.2V.
The MAX1366/MAX1368 perform analog-to-digital con-
versions using a single-bit, 3rd-order, sigma-delta mod-
ulator. The sigma-delta modulator converts the input
signal into a digital pulse train whose average duty
cycle represents the digitized signal information. The
modulator quantizes the input signal at a much higher
sample rate than the bandwidth of the input. The
MAX1366/MAX1368 modulator provides 3rd-order fre-
quency shaping of the quantization noise resulting from
the single-bit quantizer. The modulator is fully differen-
tial for maximum signal-to-noise ratio and minimum sus-
ceptibility to power-supply noise. A single-bit data
stream is then presented to the digital filter to remove
the frequency-shaped quantization noise.
The MAX1366/MAX1368 contain an on-chip digital low-
pass filter that processes the data stream from the
modulator using a SINC
The SINC
periods (4 x 200ms). The MAX1366/MAX1368 have
25% overrange capability built into the modulator and
digital filter. The digital filter is optimized for the f
equal to 4.9152MHz. The frequency response of the
SINC
where N is the oversampling ratio, and f
data rate = 5Hz.
Figure 1 shows the filter frequency response. The
SINC
times the first notch frequency (5Hz). The oversampling
Internal Analog Input/Reference Buffers
4
4
Microcontroller-Interface, 4.5-/3.5-Digit Panel
filter is calculated as follows:
characteristic -3dB cutoff frequency is 0.228
4
filter has a settling time of four output data
H z
H f
( )
( )
______________________________________________________________________________________
=
=
N




1



1 1
N
4







sin( ) x
(
sin
(
response:
1
−
x
sin
−
Z



Z
N
−
−






N
1
π
f
4
π
)
m
)
f
f




m
f
Filter Characteristics
4






Digital Filtering







4
m
Modulator
= N x output
Meters with 4–20mA Output
CLK
ratio (OSR) for the MAX1368 is 128 and the OSR for the
MAX1366 is 1024. The output data rate for the digital fil-
ter corresponds to the positioning of the first notch of
the filter’s frequency response. The notches of the
SINC
frequency. The SINC
better than 100dB at these notches. For example, 50Hz
is equal to 10 times the first notch frequency and 60Hz
is equal to 12 times the first notch frequency. For large
step changes at the input, allow a settling time of
800ms before valid data is read.
Configure the MAX1366/MAX1368 to use either the
internal oscillator or an externally applied clock to drive
the modulator, filter, and DAC. Set the EXTCLK bit in
the control register to zero to put the device in internal
clock mode. Set the EXTCLK bit to one to put the
device in external clock mode. When using the internal
oscillator, connect CLK to GND or DV
MAX1366/MAX1368 operate with a 4.9152MHz clock to
achieve maximum rejection of 50Hz/60Hz common-
mode, power-supply, and normal-mode noise.
The MAX1366/MAX1368 contain an internal oscillator.
The power-up condition for the MAX1366/MAX1368 is
internal clock operation with the EXTCLK bit in the con-
trol register equal to zero. Using the internal oscillator
saves board space by removing the need for an exter-
nal clock source.
For external clock operation, set the EXTCLK bit in the
control register to one and drive CLK with a 4.9152MHz
Figure 1. Frequency Response of the SINC
4
filter are repeated at multiples of the first notch
-120
-160
-200
-40
-80
0
0
10
4
20
FREQUENCY (Hz)
filter provides an attenuation of
30
40
External-Clock Mode
Internal Clock Mode
4
Filter (Notch at 60Hz)
50
Clock Modes
60
DD
. The
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