25C320/SN Microchip Technology, 25C320/SN Datasheet - Page 10

• Manufacturer Part Number: 25C320/SN
• Description: IC EEPROM 32KBIT 3MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25C320/SN

• Memory Size: 32K (4K x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 3MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 4K X 8
• Ic Interface Type: SPI
• Clock Frequency: 3MHz
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25AA320/25LC320/25C320
3.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX320 is busy with a write operation. When set to a
‘
in progress. This bit is read-only.
FIGURE 3-6:
DS21227F-page 10
1
WPEN
’, a write is in progress; when set to a ‘
SCK
SO
CS
7
SI
Read Status Register Instruction
(RDSR)
X
6
X
5
0
0
READ STATUS REGISTER TIMING SEQUENCE
X
4
0
1
BP1
High-Impedance
3
0
2
Instruction
BP0
2
0
3
0
WEL
4
0
1
’, no write is
1
5
WIP
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘
allows writes to the array, when set to a ‘
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the STA-
TUS register. This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for the RDSR timing sequence.
7
8
6
9
Data from STATUS Register
10
5
11
4
12
3
© 2008 Microchip Technology Inc.
13
2
14
1
15
0
1
0
’, the latch
’, the latch