AT88SC0404CA-PU Atmel, AT88SC0404CA-PU Datasheet - Page 20

• Manufacturer Part Number: AT88SC0404CA-PU
• Description: IC EEPROM 4KBIT 4MHZ 8DIP
• Manufacturer: Atmel
• Series: CryptoMemory®r

Specifications of AT88SC0404CA-PU

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 4MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• For Use With: AT88SC-SDK1 - KIT TUEMA DK CRYPTOMEM SMARTCARDAT88SC-DK1 - KIT DEV FOR AT88SCXXXXC FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.8. Device Configuration Register (DCR)
8664C–CRYPT–01/10
This 8-bit register allows selection of the following device configuration options (active low). The values programmed
have an immediate effect on the logic of the device. The default value is “1” for each bit.
Figure 8. Device Configuration Register (DCR)
SME – Supervisor Mode Enable
Asserting this bit (SME = “0”) enables supervisor mode for Write 7 password such that verifying Write 7 password
grants read and write accesses to all password sets and PACs. Verifying Write 7 password does not grant access to
other passwords when this bit is not asserted (SME = “1”).
UCR – Unlimited Checksum Reads
Asserting this bit (UCR = “0”) allows unlimited number of checksum reads without requiring a new authentication. Not
asserting this bit (UCR = “1”) limits the read of checksum to one attempt after which the device resets the crypto
algorithm after executing the Read Checksum command.
UAT – Unlimited Authentication Trials
Asserting this bit (UAT = “0”) disables the Authentication Attempts Counter (AAC) thus allowing unlimited authentication
attempts. The AAC decrements after each unsuccessful attempt but the internal logic ignores it value. Asserting this bit
also prevents reset of the crypto algorithm after reading the MAC in encryption mode. The UAT bit does not affect the
Password Attempts Counter.
ETA – Eight Trials Allowed
Asserting this bit (ETA = “0”) extends the trials limit to eight incorrect attempts to authenticate or verify a password. The
counter (AAC or PAC) will decrement ($FF, $FE, $FC, $F8, $F0, $E0, $C0, $80, $00) with each incorrect attempt.
Disabling this bit (ETA = “1”) limits authentication and password verification trials to only four incorrect attempts ($FF,
$EE, $CC, $88, $00).
CS0 – CS3: Programmable Chip Select (only relevant in synchronous protocol)
The four most significant bits (b4 – b7) of every command comprise the Chip Select Address. All Atmel
CryptoMemory
second Chip Select Address programmed into CS0-CS3 of the Device Configuration Register. By programming each
device to a unique Chip Select Address, it is possible to connect up to 15 devices on the same Serial Data bus and
communicate individually to each. Global communications to all devices sharing the bus is accomplished using the
default Chip Select Address $B.
Bit 7
SME
®
devices will respond to the default Chip Select Address of $B (1011). Each device also responds to a
Bit 6
UCR
Bit 5
UAT
Atmel AT88SC0104/0204/0404/0808/CA
Bit 4
ETA
Bit 3
CS3
Bit 2
CS2
Bit 1
CS1
Bit 0
CS0
19
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