24LC515-I/P Microchip Technology, 24LC515-I/P Datasheet - Page 5

• Manufacturer Part Number: 24LC515-I/P
• Description: IC EEPROM 512KBIT 400KHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 24LC515-I/P

• Memory Size: 512K (64K x 8)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 64 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 24LC515I/P; Q1207932

2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
The A0, A1 inputs are used by the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
The A2 input is non-configurable Chip Select. This pin
must be tied to V
2.3
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
© 2008 Microchip Technology Inc.
Name PDIP SOIJ
SDA
SCL
V
V
WP
A0
A1
A2
SS
CC
PIN DESCRIPTIONS
A0, A1 Chip Address Inputs
A2 Chip Address Input
Serial Data (SDA)
1
2
3
4
5
6
7
8
CC
CC
1
2
3
4
5
6
7
8
PIN FUNCTION TABLE
(typical 10 kΩ for 100 kHz, 2 kΩ for
in order for this device to operate.
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard wired to
logical 1 state (V
will not operate with this pin
left floating or held to logical 0
(V
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+2.5 to 5.5V (24FC515)
SS
).
Function
CC
). Device
24AA515/24LC515/24FC515
2.4
This input is used to synchronize the data transfer from
and to the device.
2.5
This pin must be connected to either V
to V
write operations are inhibited but read operations are
not affected.
3.0
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
SS
, write operations are enabled. If tied to V
Serial Clock (SCL)
Write-Protect (WP)
FUNCTIONAL DESCRIPTION
DS21673G-page 5
SS
or V
CC
. If tied
CC
,