ALFAT-SC-340 GHI Electronics, ALFAT-SC-340 Datasheet - Page 14

• Manufacturer Part Number: ALFAT-SC-340
• Description: Processors - Application Specialized FILE SYSTEM SoC with DUAL USB HOST & SD
• Manufacturer: GHI Electronics
• Type: File Systemsr

Specifications of ALFAT-SC-340

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: ALFAT
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 24 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Interface Type: I2C, SPI, UART
• Part # Aliases: GHI-ALFAT-SC-340

SPI interface uses four hardware signals:
Note: ALFAT access reference code library, available with ALFAT's downloads, provides an
example how to use SPI interface.
Sending and receiving data to and from ALFAT over SPI is performed through frame
transactions which is a layer that resides between the actual SPI data bus and the
communication stream (commands, responses, data). It is important to know that SPI
frame transaction layer is independent from how ALFAT commands work.
4.3. SPI Interface Mode
GHI Electronics
Rev. 1.13
Communication Stream
UART configurations
Write Transaction
Request Frame
The frame consists of two parts, a header and payload.
Frame Transaction
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SPI_SSEL: ALFAT Chip Select.
SPI_MOSI: ALFAT Data in.
SPI_MISO: ALFAT Data out.
SPI_BUSY: This should be monitored while sending data to ALFAT. When it is high,
no more data should be exchanged with ALFAT till it gets low.
SPI Bus
The default baud rate is 115200. The maximum tested baud rate is 3M. To
change the baud rate use B command.
Data bits: 8
Parity: None
Stop bit: 1
The header consists of three bytes. The first byte is the frame type, the second
and the third bytes are 16-bit transaction length (Not including the header).
Payload: This is actual transaction payload needed to be sent to ALFAT. The
payload section size MUST match the declared in the transaction size field.
01
08
Write Frame: @ M:\TES
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ALFAT access interface
ALFAT SoC Processor
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