BR24L02FJ-WE2 Rohm Semiconductor, BR24L02FJ-WE2 Datasheet - Page 13

IC EEPROM 2KBIT 400KHZ 8SOP

BR24L02FJ-WE2

Manufacturer Part Number
BR24L02FJ-WE2
Description
IC EEPROM 2KBIT 400KHZ 8SOP
Manufacturer
Rohm Semiconductor
Datasheet

Specifications of BR24L02FJ-WE2

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
2K (256 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOPJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
BR24L02FJ-WE2
BR24L02FJ-WE2TR

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
BR24L02FJ-WE2
Manufacturer:
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Quantity:
1 465
Part Number:
BR24L02FJ-WE2
Manufacturer:
ROHM
Quantity:
10 054
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BR24L02FJ-WE2
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20 000
Cautions on microcontroller connection
Rs
In I
SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This controls over
current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of
protection of SDA terminal against surge. Therefore, even when SDA port is open drain input / output, Rs can be used.
Maximum value of Rs
The maximum value of Rs is determined by the following relations.
Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and
instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be
satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current
to EEPROM 10mA or below.
(1) SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
(2) The bus electric potential
2
C BUS, it is recommended that SDA port is of open drain input /output. However, when to use CMOS input / output of tri state to
And AC timing should be satisfied even when SDA rise time is late.
sufficiently secure the input "L" level (V
V
IL
Microcontroller
Fig.53 I/O circuit diagram
"H" output
Microcontroller
Microcontroller
R
Fig.55 I/O circuit diagram
PU
Fig.56 I/O circuit diagram
A
V
CC
R
to be determined by Rpu and Rs at the moment when EEPROM outputs "L" to SDA bus should
S
R
Bus line
capacity CBUS
Over current I
PU
R
EEPROM
PU
I
R
OL
S
A
R
S
IL
) of microcontroller including recommended noise margin 0.1Vcc.
EEPROM
EEPROM
"L" output
V
OL
13/16
Example) When Vcc = 3V, V
SCL
SDA
Example) When Vcc = 3V, I = 10mA,
R
V
"H" output of microcontroller
R
S
CC
S
(V
from (2),
≤ I
CC
R
R
V
R
S
S
CC
I
-V
PU
≤ 1.67 [k ]
OL
R
+R
V
S
0.3×3-0.4-0.1×3
) × R
IL
Fig.54 Input / output collision timing
≥ 300 [ ]
S
1.1×3-0.3×3
-V
1.1V
Over current flows to SDA line by "H" output of
microcontroller and "L" output of EEPROM.
10×10
OL
S
-0.1V
CC
3
+ V
-V
IL
-3
OL
IL
CC
= 0.3Vcc, V
+0.1V
"L" output of EEPROM
× R
ACK
× 20×10
CC
PU
≤ V
OL
IL
3
= 0.4V, R
PU
= 20k ,

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